source: rtems/cpukit/score/cpu/riscv

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(edit) @d7a48e1   Oct 6, 2020, 5:39:44 AM Sebastian Huber rtems: Improve RTEMS_NO_RETURN attribute Provide RTEMS_NO_RETURN also …
(edit) @48dd7b8c   Jun 29, 2020, 7:35:08 PM kinsey.moore score: Add CPU_USE_LIBC_INIT_FINI_ARRAY This introduces the …
(edit) @f4fda72   Nov 29, 2019, 6:01:00 PM Sebastian Huber Regenerate headers.am 5
(edit) @a4c5da6   Nov 11, 2019, 11:06:27 AM Hesham.Almatary riscv: preliminarily support for libdl Support for targets compiled … 5
(edit) @71f9098   Mar 27, 2019, 9:38:56 AM andreas.dachsberger doxygen: score: Add RISC-V CPU architecture group Update #3706. 5
(edit) @5526527e   Mar 25, 2019, 9:45:25 AM Sebastian Huber score: Rename ScoreCPU Doxygen group Update #3706. 5
(edit) @3fe2155   Feb 1, 2019, 9:00:36 AM Sebastian Huber Remove superfluous <rtems/system.h> includes 5
(edit) @feea03b6   Feb 27, 2019, 9:53:30 AM Sebastian Huber Remove explicit file names from @file This makes the @file … 5
(edit) @9399473c   Feb 2, 2019, 10:03:13 AM Sebastian Huber riscv: Fix misaligned access in context validate 5
(edit) @d3d4e77   Jan 18, 2019, 11:37:55 AM Jiri Gaisler riscv: add griscv bsp Update #3678. 5
(edit) @9b2b389   Jan 18, 2019, 5:00:47 PM Jiri Gaisler grlib: use cpu-independent routines for uncached access Update #3678. 5
(edit) @b9ffc41c   Jan 8, 2019, 8:50:50 AM Sebastian Huber riscv: Enable robust thread dispatch It must be enabled, since the … 5
(edit) @2548d14   Sep 10, 2018, 3:38:14 PM Sebastian Huber build: Include header.am in cpukit/Makefile.am Include all … 5
(edit) @637546a   Oct 5, 2018, 6:12:40 PM Sebastian Huber build: Merge score/cpu/*/Makefile.am 5
(edit) @68e1ccc   Sep 11, 2018, 4:30:20 AM Sebastian Huber build: Remove specialized CPPFLAGS 5
(edit) @8776bb9   Sep 26, 2018, 4:34:54 AM Sebastian Huber score: Remove CPU_PROVIDES_IDLE_THREAD_BODY Remove the … 5
(edit) @27bbc05   Aug 2, 2018, 12:49:01 PM Sebastian Huber score: Remove CPU_PARTITION_ALIGNMENT Use the CPU_SIZEOF_POINTER … 5
(edit) @28b8cf9b   Aug 2, 2018, 7:41:08 AM Sebastian Huber riscv: Fix CPU_ALIGNMENT Update #3433. 5
(edit) @cfc9573   Jul 27, 2018, 12:47:17 PM Sebastian Huber riscv: Rework CPU counter support Update #3433. 5
(edit) @6b9ef09   Jul 20, 2018, 8:57:59 AM Sebastian Huber riscv: Add CLINT and PLIC support The CLINT and PLIC need some … 5
(edit) @c2670de   Jul 20, 2018, 7:07:40 AM Sebastian Huber riscv: Use wfi instruction for idle task Update #3433. 5
(edit) @8db3f0e   Jul 19, 2018, 10:11:19 AM Sebastian Huber riscv: Rework exception handling Remove … 5
(edit) @5694b0c   Jul 19, 2018, 8:15:53 AM Sebastian Huber riscv: New CPU_Exception_frame Use the CPU_Interrupt_frame for the … 5
(edit) @d779a1e2   Jul 19, 2018, 7:35:54 AM Sebastian Huber riscv: Add exception codes Update #3433. 5
(edit) @3a646426   Jul 19, 2018, 10:53:34 AM Sebastian Huber score: Add _CPU_Instruction_illegal() On some … 5
(edit) @b74353e   Jul 20, 2018, 6:06:46 AM Sebastian Huber score: Add _CPU_Instruction_no_operation() This helps to reduce the … 5
(edit) @42f2fdfd   Jul 20, 2018, 5:56:43 AM Sebastian Huber score: Move context validation declarations The context validation … 5
(edit) @248ca7a   Jul 20, 2018, 7:10:29 AM Sebastian Huber score: Remove obsolete CPU port defines 5
(edit) @bca36d9   Jul 6, 2018, 9:07:20 AM Sebastian Huber riscv: Add LADDR assembler define An address must be loaded to a … 5
(edit) @dd32e2b2   Jul 6, 2018, 6:12:40 AM Sebastian Huber riscv: Implement CPU counter Update #3433. 5
(edit) @e755782   Jul 3, 2018, 7:54:47 AM Sebastian Huber riscv: Clear reservations See also RISC-V User-Level ISA V2.3, … 5
(edit) @e07b51a7   Jul 2, 2018, 1:21:36 PM Sebastian Huber riscv: Fix fcsr initialization Update #3433. 5
(edit) @79d69ae   Jun 29, 2018, 10:08:01 AM Sebastian Huber riscv: Fix SMP context switch support Update #3433. 5
(edit) @109bc1c7   Jun 29, 2018, 6:07:02 AM Sebastian Huber riscv: Add SMP context switch support Update #3433. 5
(edit) @52352387   Jun 28, 2018, 7:32:26 AM Sebastian Huber riscv: Add floating-point support Update #3433. 5
(edit) @995e91e8   Jun 28, 2018, 6:21:44 AM Sebastian Huber riscv: Fix global construction Update #3433. 5
(edit) @694e79a0   Jun 28, 2018, 6:20:47 AM Sebastian Huber riscv: Add TLS support Update #3433. 5
(edit) @afb60eb   Jun 27, 2018, 12:46:06 PM Sebastian Huber riscv: Remove dead code Update #3433. 5
(edit) @e43994d   Jun 27, 2018, 8:05:50 AM Sebastian Huber riscv: Optimize context switch and interrupts Save/restore … 5
(edit) @a8188730   Jun 27, 2018, 7:43:39 AM Sebastian Huber riscv: Fix _CPU_Context_Initialize() prototype Update #3433. 5
(edit) @dffc08c   Jun 28, 2018, 11:55:29 AM Sebastian Huber riscv: Fix interrupt save/restore Update #3433. 5
(edit) @40f81ce6   Jun 27, 2018, 10:18:09 AM Sebastian Huber riscv: Implement _CPU_Context_validate() Update #3433. 5
(edit) @71af1a4   Jun 27, 2018, 10:17:21 AM Sebastian Huber riscv: Make some CPU port defines visible to asm Move SREG and LREG … 5
(edit) @8f035cb   Jun 27, 2018, 6:57:08 AM Sebastian Huber riscv: Implement _CPU_Context_volatile_clobber() Update #3433. 5
(edit) @b706b4a   Jun 27, 2018, 6:54:13 AM Sebastian Huber riscv: Remove mstatus from thread context The mstatus register … 5
(edit) @2987c4f   Jun 27, 2018, 6:43:25 AM Sebastian Huber riscv: Remove x8 initialization The RISC-V psABI … 5
(edit) @04698eb   Jun 27, 2018, 6:42:48 AM Sebastian Huber riscv: Properly align the thread stack Update #3433. 5
(edit) @a49a3c8e   Jun 27, 2018, 6:37:34 AM Sebastian Huber riscv: Do not clear thread context Do not clear the complete thread … 5
(edit) @9510742   Jun 27, 2018, 6:35:13 AM Sebastian Huber riscv: Fix CPU_STACK_ALIGNMENT According to the RISC-V psABI … 5
(edit) @98f051e   Jun 27, 2018, 6:08:10 AM Sebastian Huber riscv: Remove RISCV_GCC_RED_ZONE_SIZE The current ABI says that there … 5
(edit) @9704d86f   Jun 26, 2018, 6:53:28 AM Sebastian Huber riscv: Enable interrupts during dispatch after ISR The code sequence … 5
(edit) @0fd8287   Jun 26, 2018, 5:15:28 AM Sebastian Huber riscv: Add _CPU_Get_current_per_CPU_control() Update #3433. 5
(edit) @3be4478f   Jun 26, 2018, 5:13:28 AM Sebastian Huber riscv: Avoid namespace pollution Remove <rtems/score/riscv-utility.h> … 5
(edit) @bc3bdf2   Jun 28, 2018, 12:59:38 PM Sebastian Huber riscv: Optimize and fix interrupt disable/enable Use the atomic read … 5
(edit) @2086948a   May 11, 2018, 4:54:59 AM Sebastian Huber riscv: Add dummy SMP support Update #3433. 5
(edit) @7c3b0df1   Jun 22, 2018, 11:30:49 AM Sebastian Huber riscv: Implement ISR set/get level Fix prototypes. Update #3433. 5
(edit) @9b2ef07f   Jun 22, 2018, 11:30:21 AM Sebastian Huber bsp/riscv: Load global pointer Update #3433. 5
(edit) @52f4fb6   Jun 26, 2018, 5:48:06 AM Sebastian Huber riscv: Format assembler files Use tabs to match the GCC generated … 5
(edit) @511dc4b   Jun 19, 2018, 7:09:51 AM Sebastian Huber Rework initialization and interrupt stack support Statically … 5
(edit) @c8df844   Jun 19, 2018, 12:59:51 PM Sebastian Huber score: Add CPU_INTERRUPT_STACK_ALIGNMENT Add CPU port define for the … 5
(edit) @65f868c   May 23, 2018, 12:17:25 PM Sebastian Huber Add _CPU_Counter_frequency() Add rtems_counter_frequency() API … 5
(edit) @f35c3be9   Apr 16, 2018, 5:34:18 AM Sebastian Huber Remove register keyword from public header files The following code … 5
(edit) @5b88ec5   Mar 8, 2018, 11:23:21 PM joel riscv/include/rtems/score/types.h: Eliminate this file Updates #3327. 5
(edit) @2afb22b   Dec 23, 2017, 7:18:56 AM Chris Johns Remove make preinstall A speciality of the RTEMS build system was the … 5
(edit) @c3897697   Nov 29, 2017, 4:32:18 PM joel riscv/rtems/score/cpu.h: Use RTEMS_NO_RETURN not deprecated … 5
(add) @11ff3a9   Oct 27, 2017, 4:18:40 AM Hesham Almatary cpukit: RISC-V - make riscv32 code work for riscv64 - v2 * Use … 5
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