Add SMP support for RISC-V

[Sebastian Huber]

The project includes the following tasks:

• add CPU counter support
• add context validation code
• add BSP support for Qemu
• add support for device tree provided by Qemu
• fix all unexpected test suite failures running on Qemu
• add build system support to enable an SMP build
• add SMP implementation

[Sebastian Huber <sebastian.huber@…>]

In 7b7e340/rtems-tools:

tester: Add rv64imafd_medany.ini

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 9e3bb45/rtems:

bsp/riscv_generic: New linker command file

This linker command file is based on the "riscv64-rtems5-ld --verbose"
output.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 41e2295/rtems:

bsp/riscv_generic: Use standard optimization flags

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 6f5d88a/rtems:

bsp/riscv_generic: Rename to "riscv"

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In f3da074a/rtems:

bsp/riscv: Add new BSP variants

The latest RISC-V tool chain introduced new multilib variants. Add
corresponding BSP variants.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 37a1fc2/rtems:

bsp/riscv: Remove unused BSP options

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 16d905f/rtems:

bsp/riscv: Add BSP options to define RAM region

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In fef0a41/rtems:

bsp/riscv: Do not clear integer registers at start

There is no need to do this.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 52f4fb6/rtems:

riscv: Format assembler files

Use tabs to match the GCC generated assembler output.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In b0ee789/rtems:

bsp/riscv: Use memset() to clear .bss

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 9b2ef07f/rtems:

bsp/riscv: Load global pointer

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 7c3b0df1/rtems:

riscv: Implement ISR set/get level

Fix prototypes.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 853c5ef/rtems:

build: Enable RISC-V SMP build

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 2086948/rtems:

riscv: Add dummy SMP support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In fe2cd01/rtems:

bsp/riscv: Add device tree support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 5f5c450/rtems:

bsp/riscv: Add SMP startup synchronization

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In c558cc4/rtems:

bsp/riscv: Fix vector table for lp64

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 1232cd46/rtems:

bsp/riscv: Add device tree support for console

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In cdfed94f/rtems:

bsp/riscv: Rework clock driver

Use device tree provided timebase frequency. Do not write to read-only
mtime register.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In ff7b104/rtems:

bsp/riscv: Remove bsp_interrupt_handler_default()

It duplicated the default implementation.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In bc3bdf2/rtems:

riscv: Optimize and fix interrupt disable/enable

Use the atomic read and clear operation to disable interrupts.

Do not write the complete mstatus. Instead, set only the MIE bit
depending on the level parameter.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 3be4478f/rtems:

riscv: Avoid namespace pollution

Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 0fd8287/rtems:

riscv: Add _CPU_Get_current_per_CPU_control()

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 9704d86f/rtems:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 98f051e/rtems:

riscv: Remove RISCV_GCC_RED_ZONE_SIZE

The current ABI says that there is no stack red zone:

​https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 9510742/rtems:

riscv: Fix CPU_STACK_ALIGNMENT

According to the RISC-V psABI

​https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

the stack alignment is 128 bits (16 bytes).

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In a49a3c8e/rtems:

riscv: Do not clear thread context

Do not clear the complete thread context. Initialize only the necessary
members. The Context_Control::is_executing member must be preserved
across _CPU_Context_Initialize() calls.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 04698eb/rtems:

riscv: Properly align the thread stack

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 2987c4f/rtems:

riscv: Remove x8 initialization

The RISC-V psABI

​https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

does not mention that this is a frame pointer.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In b706b4a/rtems:

riscv: Remove mstatus from thread context

The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 8f035cb/rtems:

riscv: Implement _CPU_Context_volatile_clobber()

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 71af1a4/rtems:

riscv: Make some CPU port defines visible to asm

Move SREG and LREG assembler defines to <rtems/score/asm.h>.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 40f81ce6/rtems:

riscv: Implement _CPU_Context_validate()

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In dffc08c/rtems:

riscv: Fix interrupt save/restore

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In a8188730/rtems:

riscv: Fix _CPU_Context_Initialize() prototype

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In e43994d/rtems:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In afb60eb/rtems:

riscv: Remove dead code

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 694e79a0/rtems:

riscv: Add TLS support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 995e91e8/rtems:

riscv: Fix global construction

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 5235238/rtems:

riscv: Add floating-point support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 109bc1c7/rtems:

riscv: Add SMP context switch support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 79d69ae/rtems:

riscv: Fix SMP context switch support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 79d69ae/rtems:

riscv: Fix SMP context switch support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In b36bf5b/rtems:

score: Increase PER_CPU_CONTROL_SIZE_APPROX

Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In e07b51a7/rtems:

riscv: Fix fcsr initialization

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In e755782/rtems:

riscv: Clear reservations

See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store?-Conditional Instructions".

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 6418c91d/rtems:

Update config.guess and config.sub

Update via:

wget -O config.guess '​https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD'
wget -O config.sub '​https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD'

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In dd32e2b2/rtems:

riscv: Implement CPU counter

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In bca36d9/rtems:

riscv: Add LADDR assembler define

An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 31f90a2/rtems:

bsp/riscv: Simplify printk() support

This is a prepartion to add NS16550 driver support to the console
driver.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 1a19239/rtems:

bsp/riscv: Add console support for NS16550 devices

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 3a646426/rtems:

score: Add _CPU_Instruction_illegal()

On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In d779a1e2/rtems:

riscv: Add exception codes

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 5694b0c/rtems:

riscv: New CPU_Exception_frame

Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 8db3f0e/rtems:

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 7fe4855/rtems:

bsp/riscv: Fix HTIF warnings

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 791d9ac5/rtems:

bsp/riscv: Disable HTIF support by default

The HTIF is a legacy machinery.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 3a263a9b/rtems:

bsp/riscv: Add and use riscv_fdt_get_address()

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In dda6e06/rtems:

bsp/riscv: Add reset via for SiFive? Test Finisher

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In f5fd8eb/rtems:

bsps/riscv: Update linker-symbols.h

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In d3d115a/rtems-tools:

tester: Add use virt machine for rv64imafd_medany

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In c2670de/rtems:

riscv: Use wfi instruction for idle task

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 6b9ef09/rtems:

riscv: Add CLINT and PLIC support

The CLINT and PLIC need some per-processor state.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 447fd89/rtems:

bsp/riscv: Add basic SMP startup

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 6552ba8/rtems:

bsp/riscv: Use CPU counter btimer

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In bd560386/rtems:

bsp/riscv: Add simple SMP support to clock driver

This is a hack. The clock interrupt should be handled by each hart.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In adede135/rtems:

bsp/riscv: Add PLIC support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 581a0f88/rtems:

bsp/riscv: Use interrupt driven NS16550 driver

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 65f52d0/rtems:

samples/minimum: Use default interrupt stack size

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In cfc9573/rtems:

riscv: Rework CPU counter support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 44c2d393/rtems:

bsp/riscv: Fix inter-processor interrupts

The previous version worked only on a patched Qemu. Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In d906ce3/rtems:

libtests: Use CONFIGURE_INIT_TASK_TABLE_SIZE

Using CONFIGURE_MINIMUM_TASK_STACK_SIZE increases also the interrupt
stack size. This is an issue on some BSPs. Use
CONFIGURE_INIT_TASK_TABLE_SIZE instead.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 48cbd63/rtems:

bsp/riscv: Fix clock driver

Do not assume that mtime is zero at boot time.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 529154b/rtems:

bsp/riscv: Initialize FPU depending on ISA

Initialize fcsr to zero for a defined rounding mode.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 56b0387/rtems:

bsp/riscv: Add NS16750 support to console driver

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In dee2ebb/rtems:

bsp/riscv: Remove unused variable

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 3d11c1e/rtems:

bsp/riscv: Fix a synchronization issue for PLIC

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 28b8cf9b/rtems:

riscv: Fix CPU_ALIGNMENT

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In d909c5f/rtems-docs:

cpu-supplement: Add RISC-V chapter

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 24326a8/rtems-docs:

user: Add RISC-V BSP section

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 4c740de/rtems:

bsp/riscv: Fix build with RTEMS_SMP undefined

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 141d502/rtems:

bsp/riscv: Add missing BSP variant

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 5d957c9/rtems-tools:

tester: Add RISC-V support to BSP builder

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In d343f83/rtems-tools:

tester: Exclude SMP build of some RISC-V BSPs

It makes no sense to build BSPs without support for atomic instructions
with SMP enabled.

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 01600ac/rtems-source-builder:

5: Update tools for RISC-V BSP builder support

Update #3433.

[Sebastian Huber <sebastian.huber@…>]

In 142770b/rtems-docs:

c-user: SMP is supported on RISC-V

Update #3433.

[Sebastian Huber]

The RISC-V SMP support is now in a good shape.

[Sebastian Huber <sebastian.huber@…>]

In b9ffc41c/rtems:

riscv: Enable robust thread dispatch

It must be enabled, since the context switch code does not save/restore
the interrupt status.

Update #3433.