#3433 closed project (fixed)

Add SMP support for RISC-V

Reported by: Sebastian Huber Owned by: Sebastian Huber
Priority: normal Milestone: 5.1
Component: arch/riscv Version: 5
Severity: normal Keywords:
Cc: Blocked By: #3452, #3453, #3459
Blocking:

Description

The project includes the following tasks:

  • add CPU counter support
  • add context validation code
  • add BSP support for Qemu
  • add support for device tree provided by Qemu
  • fix all unexpected test suite failures running on Qemu
  • add build system support to enable an SMP build
  • add SMP implementation

Change History (92)

comment:1 Changed on May 25, 2018 at 7:11:14 AM by Sebastian Huber

Owner: set to Sebastian Huber
Status: newaccepted

comment:2 Changed on Jun 13, 2018 at 8:45:14 AM by Sebastian Huber

Blocked By: 3452, 3453 added

comment:3 Changed on Jun 18, 2018 at 6:30:48 AM by Sebastian Huber

Blocked By: 3459 added

comment:4 Changed on Jun 29, 2018 at 8:31:10 AM by Sebastian Huber <sebastian.huber@…>

In 7b7e340/rtems-tools:

tester: Add rv64imafd_medany.ini

Update #3433.

comment:5 Changed on Jun 29, 2018 at 9:54:24 AM by Sebastian Huber <sebastian.huber@…>

In 9e3bb45/rtems:

bsp/riscv_generic: New linker command file

This linker command file is based on the "riscv64-rtems5-ld --verbose"
output.

Update #3433.

comment:6 Changed on Jun 29, 2018 at 9:54:45 AM by Sebastian Huber <sebastian.huber@…>

In 41e2295/rtems:

bsp/riscv_generic: Use standard optimization flags

Update #3433.

comment:7 Changed on Jun 29, 2018 at 9:54:56 AM by Sebastian Huber <sebastian.huber@…>

In 6f5d88a/rtems:

bsp/riscv_generic: Rename to "riscv"

Update #3433.

comment:8 Changed on Jun 29, 2018 at 9:55:06 AM by Sebastian Huber <sebastian.huber@…>

In f3da074a/rtems:

bsp/riscv: Add new BSP variants

The latest RISC-V tool chain introduced new multilib variants. Add
corresponding BSP variants.

Update #3433.

comment:9 Changed on Jun 29, 2018 at 9:55:17 AM by Sebastian Huber <sebastian.huber@…>

In 37a1fc2/rtems:

bsp/riscv: Remove unused BSP options

Update #3433.

comment:10 Changed on Jun 29, 2018 at 9:55:27 AM by Sebastian Huber <sebastian.huber@…>

In 16d905f/rtems:

bsp/riscv: Add BSP options to define RAM region

Update #3433.

comment:11 Changed on Jun 29, 2018 at 9:55:50 AM by Sebastian Huber <sebastian.huber@…>

In fef0a41/rtems:

bsp/riscv: Do not clear integer registers at start

There is no need to do this.

Update #3433.

comment:12 Changed on Jun 29, 2018 at 9:56:01 AM by Sebastian Huber <sebastian.huber@…>

In 52f4fb6/rtems:

riscv: Format assembler files

Use tabs to match the GCC generated assembler output.

Update #3433.

comment:13 Changed on Jun 29, 2018 at 9:56:11 AM by Sebastian Huber <sebastian.huber@…>

In b0ee789/rtems:

bsp/riscv: Use memset() to clear .bss

Update #3433.

comment:14 Changed on Jun 29, 2018 at 9:56:22 AM by Sebastian Huber <sebastian.huber@…>

In 9b2ef07f/rtems:

bsp/riscv: Load global pointer

Update #3433.

comment:15 Changed on Jun 29, 2018 at 9:56:33 AM by Sebastian Huber <sebastian.huber@…>

In 7c3b0df1/rtems:

riscv: Implement ISR set/get level

Fix prototypes.

Update #3433.

comment:16 Changed on Jun 29, 2018 at 9:56:44 AM by Sebastian Huber <sebastian.huber@…>

In 853c5ef/rtems:

build: Enable RISC-V SMP build

Update #3433.

comment:17 Changed on Jun 29, 2018 at 9:56:56 AM by Sebastian Huber <sebastian.huber@…>

In 2086948/rtems:

riscv: Add dummy SMP support

Update #3433.

comment:18 Changed on Jun 29, 2018 at 9:57:07 AM by Sebastian Huber <sebastian.huber@…>

In fe2cd01/rtems:

bsp/riscv: Add device tree support

Update #3433.

comment:19 Changed on Jun 29, 2018 at 9:57:18 AM by Sebastian Huber <sebastian.huber@…>

In 5f5c450/rtems:

bsp/riscv: Add SMP startup synchronization

Update #3433.

comment:20 Changed on Jun 29, 2018 at 9:57:29 AM by Sebastian Huber <sebastian.huber@…>

In c558cc4/rtems:

bsp/riscv: Fix vector table for lp64

Update #3433.

comment:21 Changed on Jun 29, 2018 at 9:57:39 AM by Sebastian Huber <sebastian.huber@…>

In 1232cd46/rtems:

bsp/riscv: Add device tree support for console

Update #3433.

comment:22 Changed on Jun 29, 2018 at 9:57:50 AM by Sebastian Huber <sebastian.huber@…>

In cdfed94f/rtems:

bsp/riscv: Rework clock driver

Use device tree provided timebase frequency. Do not write to read-only
mtime register.

Update #3433.

comment:23 Changed on Jun 29, 2018 at 9:58:00 AM by Sebastian Huber <sebastian.huber@…>

In ff7b104/rtems:

bsp/riscv: Remove bsp_interrupt_handler_default()

It duplicated the default implementation.

Update #3433.

comment:24 Changed on Jun 29, 2018 at 9:58:10 AM by Sebastian Huber <sebastian.huber@…>

In bc3bdf2/rtems:

riscv: Optimize and fix interrupt disable/enable

Use the atomic read and clear operation to disable interrupts.

Do not write the complete mstatus. Instead, set only the MIE bit
depending on the level parameter.

Update #3433.

comment:25 Changed on Jun 29, 2018 at 9:58:20 AM by Sebastian Huber <sebastian.huber@…>

In 3be4478f/rtems:

riscv: Avoid namespace pollution

Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).

Update #3433.

comment:26 Changed on Jun 29, 2018 at 9:58:31 AM by Sebastian Huber <sebastian.huber@…>

In 0fd8287/rtems:

riscv: Add _CPU_Get_current_per_CPU_control()

Update #3433.

comment:27 Changed on Jun 29, 2018 at 9:58:41 AM by Sebastian Huber <sebastian.huber@…>

In 9704d86f/rtems:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

comment:28 Changed on Jun 29, 2018 at 9:58:52 AM by Sebastian Huber <sebastian.huber@…>

In 98f051e/rtems:

riscv: Remove RISCV_GCC_RED_ZONE_SIZE

The current ABI says that there is no stack red zone:

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."

Update #3433.

comment:29 Changed on Jun 29, 2018 at 9:59:03 AM by Sebastian Huber <sebastian.huber@…>

In 9510742/rtems:

riscv: Fix CPU_STACK_ALIGNMENT

According to the RISC-V psABI

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

the stack alignment is 128 bits (16 bytes).

Update #3433.

comment:30 Changed on Jun 29, 2018 at 9:59:13 AM by Sebastian Huber <sebastian.huber@…>

In a49a3c8e/rtems:

riscv: Do not clear thread context

Do not clear the complete thread context. Initialize only the necessary
members. The Context_Control::is_executing member must be preserved
across _CPU_Context_Initialize() calls.

Update #3433.

comment:31 Changed on Jun 29, 2018 at 9:59:23 AM by Sebastian Huber <sebastian.huber@…>

In 04698eb/rtems:

riscv: Properly align the thread stack

Update #3433.

comment:32 Changed on Jun 29, 2018 at 9:59:33 AM by Sebastian Huber <sebastian.huber@…>

In 2987c4f/rtems:

riscv: Remove x8 initialization

The RISC-V psABI

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

does not mention that this is a frame pointer.

Update #3433.

comment:33 Changed on Jun 29, 2018 at 9:59:44 AM by Sebastian Huber <sebastian.huber@…>

In b706b4a/rtems:

riscv: Remove mstatus from thread context

The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.

comment:34 Changed on Jun 29, 2018 at 9:59:54 AM by Sebastian Huber <sebastian.huber@…>

In 8f035cb/rtems:

riscv: Implement _CPU_Context_volatile_clobber()

Update #3433.

comment:35 Changed on Jun 29, 2018 at 10:00:04 AM by Sebastian Huber <sebastian.huber@…>

In 71af1a4/rtems:

riscv: Make some CPU port defines visible to asm

Move SREG and LREG assembler defines to <rtems/score/asm.h>.

Update #3433.

comment:36 Changed on Jun 29, 2018 at 10:00:14 AM by Sebastian Huber <sebastian.huber@…>

In 40f81ce6/rtems:

riscv: Implement _CPU_Context_validate()

Update #3433.

comment:37 Changed on Jun 29, 2018 at 10:00:25 AM by Sebastian Huber <sebastian.huber@…>

In dffc08c/rtems:

riscv: Fix interrupt save/restore

Update #3433.

comment:38 Changed on Jun 29, 2018 at 10:00:35 AM by Sebastian Huber <sebastian.huber@…>

In a8188730/rtems:

riscv: Fix _CPU_Context_Initialize() prototype

Update #3433.

comment:39 Changed on Jun 29, 2018 at 10:00:45 AM by Sebastian Huber <sebastian.huber@…>

In e43994d/rtems:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

comment:40 Changed on Jun 29, 2018 at 10:00:55 AM by Sebastian Huber <sebastian.huber@…>

In afb60eb/rtems:

riscv: Remove dead code

Update #3433.

comment:41 Changed on Jun 29, 2018 at 10:01:05 AM by Sebastian Huber <sebastian.huber@…>

In 694e79a0/rtems:

riscv: Add TLS support

Update #3433.

comment:42 Changed on Jun 29, 2018 at 10:01:16 AM by Sebastian Huber <sebastian.huber@…>

In 995e91e8/rtems:

riscv: Fix global construction

Update #3433.

comment:43 Changed on Jun 29, 2018 at 10:01:26 AM by Sebastian Huber <sebastian.huber@…>

In 5235238/rtems:

riscv: Add floating-point support

Update #3433.

comment:44 Changed on Jun 29, 2018 at 10:01:36 AM by Sebastian Huber <sebastian.huber@…>

In 109bc1c7/rtems:

riscv: Add SMP context switch support

Update #3433.

comment:45 Changed on Jun 29, 2018 at 10:09:06 AM by Sebastian Huber <sebastian.huber@…>

In 79d69ae/rtems:

riscv: Fix SMP context switch support

Update #3433.

comment:46 Changed on Jun 29, 2018 at 10:09:16 AM by Sebastian Huber <sebastian.huber@…>

In 79d69ae/rtems:

riscv: Fix SMP context switch support

Update #3433.

comment:47 Changed on Jun 29, 2018 at 10:57:42 AM by Sebastian Huber <sebastian.huber@…>

In b36bf5b/rtems:

score: Increase PER_CPU_CONTROL_SIZE_APPROX

Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets.

Update #3433.

comment:48 Changed on Jul 2, 2018 at 1:22:23 PM by Sebastian Huber <sebastian.huber@…>

In e07b51a7/rtems:

riscv: Fix fcsr initialization

Update #3433.

comment:49 Changed on Jul 6, 2018 at 5:27:22 AM by Sebastian Huber <sebastian.huber@…>

In e755782/rtems:

riscv: Clear reservations

See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store?-Conditional Instructions".

Update #3433.

comment:50 Changed on Jul 6, 2018 at 8:06:38 AM by Sebastian Huber <sebastian.huber@…>

comment:51 Changed on Jul 6, 2018 at 12:28:33 PM by Sebastian Huber <sebastian.huber@…>

In dd32e2b2/rtems:

riscv: Implement CPU counter

Update #3433.

comment:52 Changed on Jul 6, 2018 at 12:28:43 PM by Sebastian Huber <sebastian.huber@…>

In bca36d9/rtems:

riscv: Add LADDR assembler define

An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.

comment:53 Changed on Jul 6, 2018 at 12:28:54 PM by Sebastian Huber <sebastian.huber@…>

In 31f90a2/rtems:

bsp/riscv: Simplify printk() support

This is a prepartion to add NS16550 driver support to the console
driver.

Update #3433.

comment:54 Changed on Jul 6, 2018 at 12:29:04 PM by Sebastian Huber <sebastian.huber@…>

In 1a19239/rtems:

bsp/riscv: Add console support for NS16550 devices

Update #3433.

comment:55 Changed on Jul 24, 2018 at 7:13:55 AM by Sebastian Huber <sebastian.huber@…>

In 3a646426/rtems:

score: Add _CPU_Instruction_illegal()

On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.

Update #3433.

comment:56 Changed on Jul 25, 2018 at 8:10:25 AM by Sebastian Huber <sebastian.huber@…>

In d779a1e2/rtems:

riscv: Add exception codes

Update #3433.

comment:57 Changed on Jul 25, 2018 at 8:10:35 AM by Sebastian Huber <sebastian.huber@…>

In 5694b0c/rtems:

riscv: New CPU_Exception_frame

Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.

Update #3433.

comment:58 Changed on Jul 25, 2018 at 8:10:45 AM by Sebastian Huber <sebastian.huber@…>

In 8db3f0e/rtems:

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

comment:59 Changed on Jul 25, 2018 at 8:10:56 AM by Sebastian Huber <sebastian.huber@…>

In 7fe4855/rtems:

bsp/riscv: Fix HTIF warnings

Update #3433.

comment:60 Changed on Jul 25, 2018 at 8:11:06 AM by Sebastian Huber <sebastian.huber@…>

In 791d9ac5/rtems:

bsp/riscv: Disable HTIF support by default

The HTIF is a legacy machinery.

Update #3433.

comment:61 Changed on Jul 25, 2018 at 8:11:16 AM by Sebastian Huber <sebastian.huber@…>

In 3a263a9b/rtems:

bsp/riscv: Add and use riscv_fdt_get_address()

Update #3433.

comment:62 Changed on Jul 25, 2018 at 8:11:26 AM by Sebastian Huber <sebastian.huber@…>

In dda6e06/rtems:

bsp/riscv: Add reset via for SiFive? Test Finisher

Update #3433.

comment:63 Changed on Jul 25, 2018 at 8:11:37 AM by Sebastian Huber <sebastian.huber@…>

In f5fd8eb/rtems:

bsps/riscv: Update linker-symbols.h

Update #3433.

comment:64 Changed on Jul 25, 2018 at 8:11:41 AM by Sebastian Huber <sebastian.huber@…>

In d3d115a/rtems-tools:

tester: Add use virt machine for rv64imafd_medany

Update #3433.

comment:65 Changed on Jul 25, 2018 at 8:11:48 AM by Sebastian Huber <sebastian.huber@…>

In c2670de/rtems:

riscv: Use wfi instruction for idle task

Update #3433.

comment:66 Changed on Jul 25, 2018 at 8:11:58 AM by Sebastian Huber <sebastian.huber@…>

In 6b9ef09/rtems:

riscv: Add CLINT and PLIC support

The CLINT and PLIC need some per-processor state.

Update #3433.

comment:67 Changed on Jul 25, 2018 at 8:12:09 AM by Sebastian Huber <sebastian.huber@…>

In 447fd89/rtems:

bsp/riscv: Add basic SMP startup

Update #3433.

comment:68 Changed on Jul 25, 2018 at 8:12:19 AM by Sebastian Huber <sebastian.huber@…>

In 6552ba8/rtems:

bsp/riscv: Use CPU counter btimer

Update #3433.

comment:69 Changed on Jul 25, 2018 at 8:12:30 AM by Sebastian Huber <sebastian.huber@…>

In bd560386/rtems:

bsp/riscv: Add simple SMP support to clock driver

This is a hack. The clock interrupt should be handled by each hart.

Update #3433.

comment:70 Changed on Jul 25, 2018 at 8:12:40 AM by Sebastian Huber <sebastian.huber@…>

In adede135/rtems:

bsp/riscv: Add PLIC support

Update #3433.

comment:71 Changed on Jul 25, 2018 at 8:12:50 AM by Sebastian Huber <sebastian.huber@…>

In 581a0f88/rtems:

bsp/riscv: Use interrupt driven NS16550 driver

Update #3433.

comment:72 Changed on Jul 27, 2018 at 11:26:50 AM by Sebastian Huber <sebastian.huber@…>

In 65f52d0/rtems:

samples/minimum: Use default interrupt stack size

Update #3433.

comment:73 Changed on Jul 27, 2018 at 1:07:35 PM by Sebastian Huber <sebastian.huber@…>

In cfc9573/rtems:

riscv: Rework CPU counter support

Update #3433.

comment:74 Changed on Jul 27, 2018 at 1:07:45 PM by Sebastian Huber <sebastian.huber@…>

In 44c2d393/rtems:

bsp/riscv: Fix inter-processor interrupts

The previous version worked only on a patched Qemu. Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.

comment:75 Changed on Jul 31, 2018 at 5:14:14 AM by Sebastian Huber <sebastian.huber@…>

In d906ce3/rtems:

libtests: Use CONFIGURE_INIT_TASK_TABLE_SIZE

Using CONFIGURE_MINIMUM_TASK_STACK_SIZE increases also the interrupt
stack size. This is an issue on some BSPs. Use
CONFIGURE_INIT_TASK_TABLE_SIZE instead.

Update #3433.

comment:76 Changed on Aug 1, 2018 at 9:18:31 AM by Sebastian Huber <sebastian.huber@…>

In 48cbd63/rtems:

bsp/riscv: Fix clock driver

Do not assume that mtime is zero at boot time.

Update #3433.

comment:77 Changed on Aug 1, 2018 at 9:18:42 AM by Sebastian Huber <sebastian.huber@…>

In 529154b/rtems:

bsp/riscv: Initialize FPU depending on ISA

Initialize fcsr to zero for a defined rounding mode.

Update #3433.

comment:78 Changed on Aug 1, 2018 at 9:19:12 AM by Sebastian Huber <sebastian.huber@…>

In 56b0387/rtems:

bsp/riscv: Add NS16750 support to console driver

Update #3433.

comment:79 Changed on Aug 1, 2018 at 9:19:23 AM by Sebastian Huber <sebastian.huber@…>

In dee2ebb/rtems:

bsp/riscv: Remove unused variable

Update #3433.

comment:80 Changed on Aug 2, 2018 at 7:28:46 AM by Sebastian Huber <sebastian.huber@…>

In 3d11c1e/rtems:

bsp/riscv: Fix a synchronization issue for PLIC

Update #3433.

comment:81 Changed on Aug 2, 2018 at 7:44:35 AM by Sebastian Huber <sebastian.huber@…>

In 28b8cf9b/rtems:

riscv: Fix CPU_ALIGNMENT

Update #3433.

comment:82 Changed on Aug 2, 2018 at 10:53:46 AM by Sebastian Huber <sebastian.huber@…>

In d909c5f/rtems-docs:

cpu-supplement: Add RISC-V chapter

Update #3433.

comment:83 Changed on Aug 2, 2018 at 11:21:52 AM by Sebastian Huber <sebastian.huber@…>

In 24326a8/rtems-docs:

user: Add RISC-V BSP section

Update #3433.

comment:84 Changed on Aug 2, 2018 at 12:40:02 PM by Sebastian Huber <sebastian.huber@…>

In 4c740de/rtems:

bsp/riscv: Fix build with RTEMS_SMP undefined

Update #3433.

comment:85 Changed on Aug 2, 2018 at 1:33:21 PM by Sebastian Huber <sebastian.huber@…>

In 141d502/rtems:

bsp/riscv: Add missing BSP variant

Update #3433.

comment:86 Changed on Aug 6, 2018 at 7:07:27 AM by Sebastian Huber

Milestone: 6.15.1
Version: 5

comment:87 Changed on Aug 6, 2018 at 7:51:44 AM by Sebastian Huber <sebastian.huber@…>

In 5d957c9/rtems-tools:

tester: Add RISC-V support to BSP builder

Update #3433.

comment:88 Changed on Aug 7, 2018 at 5:02:03 AM by Sebastian Huber <sebastian.huber@…>

In d343f83/rtems-tools:

tester: Exclude SMP build of some RISC-V BSPs

It makes no sense to build BSPs without support for atomic instructions
with SMP enabled.

Update #3433.

comment:89 Changed on Aug 7, 2018 at 5:06:46 AM by Sebastian Huber <sebastian.huber@…>

In 01600ac/rtems-source-builder:

5: Update tools for RISC-V BSP builder support

Update #3433.

comment:90 Changed on Aug 11, 2018 at 1:44:10 PM by Sebastian Huber <sebastian.huber@…>

In 142770b/rtems-docs:

c-user: SMP is supported on RISC-V

Update #3433.

comment:91 Changed on Sep 6, 2018 at 5:16:22 AM by Sebastian Huber

Resolution: fixed
Status: acceptedclosed

The RISC-V SMP support is now in a good shape.

comment:92 Changed on Jan 9, 2019 at 9:37:21 AM by Sebastian Huber <sebastian.huber@…>

In b9ffc41c/rtems:

riscv: Enable robust thread dispatch

It must be enabled, since the context switch code does not save/restore
the interrupt status.

Update #3433.

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