Changeset 5694b0c in rtems for cpukit/score/cpu/riscv

Timestamp:
07/19/18 08:15:53 (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
8db3f0e
Parents:
d779a1e2
git-author:
Sebastian Huber <sebastian.huber@…> (07/19/18 08:15:53)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/25/18 08:07:43)
Message:

riscv: New CPU_Exception_frame

Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.

Update #3433.

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