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@a4c5da6
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11/11/19 11:06:27 |
Hesham.Almatary |
riscv: preliminarily support for libdl
Support for targets compiled …
5
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@71f9098
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03/27/19 09:38:56 |
andreas.dachsberger |
doxygen: score: Add RISC-V CPU architecture group
Update #3706.
5
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@5526527e
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03/25/19 09:45:25 |
Sebastian Huber |
score: Rename ScoreCPU Doxygen group
Update #3706.
5
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@3fe2155
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02/01/19 09:00:36 |
Sebastian Huber |
Remove superfluous <rtems/system.h> includes
5
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@feea03b6
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02/27/19 09:53:30 |
Sebastian Huber |
Remove explicit file names from @file
This makes the @file …
5
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@9399473c
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02/02/19 10:03:13 |
Sebastian Huber |
riscv: Fix misaligned access in context validate
5
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@d3d4e77
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01/18/19 11:37:55 |
Jiri Gaisler |
riscv: add griscv bsp
Update #3678.
5
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@9b2b389
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01/18/19 17:00:47 |
Jiri Gaisler |
grlib: use cpu-independent routines for uncached access
Update #3678.
5
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@b9ffc41c
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01/08/19 08:50:50 |
Sebastian Huber |
riscv: Enable robust thread dispatch
It must be enabled, since the …
5
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@2548d14
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09/10/18 15:38:14 |
Sebastian Huber |
build: Include header.am in cpukit/Makefile.am
Include all …
5
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@637546a
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10/05/18 18:12:40 |
Sebastian Huber |
build: Merge score/cpu/*/Makefile.am
5
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@68e1ccc4
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09/11/18 04:30:20 |
Sebastian Huber |
build: Remove specialized CPPFLAGS
5
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@8776bb9
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09/26/18 04:34:54 |
Sebastian Huber |
score: Remove CPU_PROVIDES_IDLE_THREAD_BODY
Remove the …
5
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@27bbc05
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08/02/18 12:49:01 |
Sebastian Huber |
score: Remove CPU_PARTITION_ALIGNMENT
Use the CPU_SIZEOF_POINTER …
5
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@28b8cf9b
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08/02/18 07:41:08 |
Sebastian Huber |
riscv: Fix CPU_ALIGNMENT
Update #3433.
5
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@cfc9573
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07/27/18 12:47:17 |
Sebastian Huber |
riscv: Rework CPU counter support
Update #3433.
5
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@6b9ef09
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07/20/18 08:57:59 |
Sebastian Huber |
riscv: Add CLINT and PLIC support
The CLINT and PLIC need some …
5
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@c2670de
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07/20/18 07:07:40 |
Sebastian Huber |
riscv: Use wfi instruction for idle task
Update #3433.
5
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@8db3f0e
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07/19/18 10:11:19 |
Sebastian Huber |
riscv: Rework exception handling
Remove …
5
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@5694b0c
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07/19/18 08:15:53 |
Sebastian Huber |
riscv: New CPU_Exception_frame
Use the CPU_Interrupt_frame for the …
5
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@d779a1e2
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07/19/18 07:35:54 |
Sebastian Huber |
riscv: Add exception codes
Update #3433.
5
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@3a646426
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07/19/18 10:53:34 |
Sebastian Huber |
score: Add _CPU_Instruction_illegal()
On some …
5
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@b74353e
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07/20/18 06:06:46 |
Sebastian Huber |
score: Add _CPU_Instruction_no_operation()
This helps to reduce the …
5
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@42f2fdfd
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07/20/18 05:56:43 |
Sebastian Huber |
score: Move context validation declarations
The context validation …
5
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@248ca7a
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07/20/18 07:10:29 |
Sebastian Huber |
score: Remove obsolete CPU port defines
5
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@bca36d9
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07/06/18 09:07:20 |
Sebastian Huber |
riscv: Add LADDR assembler define
An address must be loaded to a …
5
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@dd32e2b2
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07/06/18 06:12:40 |
Sebastian Huber |
riscv: Implement CPU counter
Update #3433.
5
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@e755782
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07/03/18 07:54:47 |
Sebastian Huber |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, …
5
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@e07b51a7
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07/02/18 13:21:36 |
Sebastian Huber |
riscv: Fix fcsr initialization
Update #3433.
5
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@79d69ae
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06/29/18 10:08:01 |
Sebastian Huber |
riscv: Fix SMP context switch support
Update #3433.
5
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@109bc1c7
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06/29/18 06:07:02 |
Sebastian Huber |
riscv: Add SMP context switch support
Update #3433.
5
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@52352387
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06/28/18 07:32:26 |
Sebastian Huber |
riscv: Add floating-point support
Update #3433.
5
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@995e91e8
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06/28/18 06:21:44 |
Sebastian Huber |
riscv: Fix global construction
Update #3433.
5
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@694e79a0
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06/28/18 06:20:47 |
Sebastian Huber |
riscv: Add TLS support
Update #3433.
5
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@afb60eb
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06/27/18 12:46:06 |
Sebastian Huber |
riscv: Remove dead code
Update #3433.
5
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@e43994d
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06/27/18 08:05:50 |
Sebastian Huber |
riscv: Optimize context switch and interrupts
Save/restore …
5
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@a8188730
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06/27/18 07:43:39 |
Sebastian Huber |
riscv: Fix _CPU_Context_Initialize() prototype
Update #3433.
5
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@dffc08c
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06/28/18 11:55:29 |
Sebastian Huber |
riscv: Fix interrupt save/restore
Update #3433.
5
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@40f81ce6
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06/27/18 10:18:09 |
Sebastian Huber |
riscv: Implement _CPU_Context_validate()
Update #3433.
5
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@71af1a4
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06/27/18 10:17:21 |
Sebastian Huber |
riscv: Make some CPU port defines visible to asm
Move SREG and LREG …
5
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@8f035cb
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06/27/18 06:57:08 |
Sebastian Huber |
riscv: Implement _CPU_Context_volatile_clobber()
Update #3433.
5
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@b706b4a
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06/27/18 06:54:13 |
Sebastian Huber |
riscv: Remove mstatus from thread context
The mstatus register …
5
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@2987c4f
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06/27/18 06:43:25 |
Sebastian Huber |
riscv: Remove x8 initialization
The RISC-V psABI
…
5
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@04698eb
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06/27/18 06:42:48 |
Sebastian Huber |
riscv: Properly align the thread stack
Update #3433.
5
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@a49a3c8e
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06/27/18 06:37:34 |
Sebastian Huber |
riscv: Do not clear thread context
Do not clear the complete thread …
5
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@9510742
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06/27/18 06:35:13 |
Sebastian Huber |
riscv: Fix CPU_STACK_ALIGNMENT
According to the RISC-V psABI
…
5
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@98f051e
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06/27/18 06:08:10 |
Sebastian Huber |
riscv: Remove RISCV_GCC_RED_ZONE_SIZE
The current ABI says that there …
5
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@9704d86f
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06/26/18 06:53:28 |
Sebastian Huber |
riscv: Enable interrupts during dispatch after ISR
The code sequence …
5
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@0fd8287
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06/26/18 05:15:28 |
Sebastian Huber |
riscv: Add _CPU_Get_current_per_CPU_control()
Update #3433.
5
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@3be4478f
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06/26/18 05:13:28 |
Sebastian Huber |
riscv: Avoid namespace pollution
Remove <rtems/score/riscv-utility.h> …
5
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@bc3bdf2
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06/28/18 12:59:38 |
Sebastian Huber |
riscv: Optimize and fix interrupt disable/enable
Use the atomic read …
5
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@2086948a
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05/11/18 04:54:59 |
Sebastian Huber |
riscv: Add dummy SMP support
Update #3433.
5
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@7c3b0df1
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06/22/18 11:30:49 |
Sebastian Huber |
riscv: Implement ISR set/get level
Fix prototypes.
Update #3433.
5
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@9b2ef07f
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06/22/18 11:30:21 |
Sebastian Huber |
bsp/riscv: Load global pointer
Update #3433.
5
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@52f4fb6
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06/26/18 05:48:06 |
Sebastian Huber |
riscv: Format assembler files
Use tabs to match the GCC generated …
5
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@511dc4b
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06/19/18 07:09:51 |
Sebastian Huber |
Rework initialization and interrupt stack support
Statically …
5
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@c8df844
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06/19/18 12:59:51 |
Sebastian Huber |
score: Add CPU_INTERRUPT_STACK_ALIGNMENT
Add CPU port define for the …
5
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@65f868c
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05/23/18 12:17:25 |
Sebastian Huber |
Add _CPU_Counter_frequency()
Add rtems_counter_frequency() API …
5
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@f35c3be9
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04/16/18 05:34:18 |
Sebastian Huber |
Remove register keyword from public header files
The following code
…
5
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@5b88ec5
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03/08/18 23:23:21 |
joel |
riscv/include/rtems/score/types.h: Eliminate this file
Updates #3327.
5
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@2afb22b
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12/23/17 07:18:56 |
Chris Johns |
Remove make preinstall
A speciality of the RTEMS build system was the …
5
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@c3897697
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11/29/17 16:32:18 |
joel |
riscv/rtems/score/cpu.h: Use RTEMS_NO_RETURN not deprecated …
5
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@11ff3a9
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10/27/17 04:18:40 |
Hesham Almatary |
cpukit: RISC-V - make riscv32 code work for riscv64 - v2
* Use …
5
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