[6b4d0b8] | 1 | /** |
---|
[1362b7a] | 2 | * @file |
---|
| 3 | * |
---|
| 4 | * @brief LM32 CPU Department Source |
---|
| 5 | * |
---|
| 6 | * This include file contains information pertaining to the LM32 |
---|
| 7 | * processor. |
---|
[6b4d0b8] | 8 | */ |
---|
| 9 | |
---|
| 10 | /* |
---|
| 11 | * COPYRIGHT (c) 1989-2008. |
---|
| 12 | * On-Line Applications Research Corporation (OAR). |
---|
| 13 | * |
---|
| 14 | * The license and distribution terms for this file may be |
---|
| 15 | * found in the file LICENSE in this distribution or at |
---|
[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
---|
[6b4d0b8] | 17 | */ |
---|
| 18 | |
---|
| 19 | #ifndef _RTEMS_SCORE_CPU_H |
---|
| 20 | #define _RTEMS_SCORE_CPU_H |
---|
| 21 | |
---|
| 22 | #ifdef __cplusplus |
---|
| 23 | extern "C" { |
---|
| 24 | #endif |
---|
| 25 | |
---|
[c98d4748] | 26 | #include <rtems/score/basedefs.h> |
---|
[89b85e51] | 27 | #include <rtems/score/lm32.h> |
---|
[6b4d0b8] | 28 | |
---|
| 29 | /* conditional compilation parameters */ |
---|
| 30 | |
---|
| 31 | /** |
---|
[1362b7a] | 32 | * Does the CPU follow the simple vectored interrupt model? |
---|
[6b4d0b8] | 33 | * |
---|
[1362b7a] | 34 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
---|
| 35 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
---|
| 36 | * table |
---|
[6b4d0b8] | 37 | * |
---|
[1362b7a] | 38 | * Port Specific Information: |
---|
[6b4d0b8] | 39 | * |
---|
[1362b7a] | 40 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 41 | */ |
---|
| 42 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
---|
| 43 | |
---|
| 44 | /** |
---|
[1362b7a] | 45 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
| 46 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
| 47 | * number (0)? |
---|
[6b4d0b8] | 48 | * |
---|
[1362b7a] | 49 | * Port Specific Information: |
---|
[6b4d0b8] | 50 | * |
---|
[1362b7a] | 51 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 52 | */ |
---|
[141e16d] | 53 | #define CPU_ISR_PASSES_FRAME_POINTER TRUE |
---|
[6b4d0b8] | 54 | |
---|
| 55 | /** |
---|
[1362b7a] | 56 | * @def CPU_HARDWARE_FP |
---|
[6b4d0b8] | 57 | * |
---|
[1362b7a] | 58 | * Does the CPU have hardware floating point? |
---|
[6b4d0b8] | 59 | * |
---|
[1362b7a] | 60 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
---|
| 61 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
---|
[6b4d0b8] | 62 | * |
---|
[1362b7a] | 63 | * If there is a FP coprocessor such as the i387 or mc68881, then |
---|
| 64 | * the answer is TRUE. |
---|
[6b4d0b8] | 65 | * |
---|
[1362b7a] | 66 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
---|
| 67 | * It indicates whether or not this CPU model has FP support. For |
---|
| 68 | * example, it would be possible to have an i386_nofp CPU model |
---|
| 69 | * which set this to false to indicate that you have an i386 without |
---|
| 70 | * an i387 and wish to leave floating point support out of RTEMS. |
---|
[6b4d0b8] | 71 | */ |
---|
| 72 | |
---|
[42e243e] | 73 | /** |
---|
[1362b7a] | 74 | * @def CPU_SOFTWARE_FP |
---|
[6b4d0b8] | 75 | * |
---|
[1362b7a] | 76 | * Does the CPU have no hardware floating point and GCC provides a |
---|
| 77 | * software floating point implementation which must be context |
---|
| 78 | * switched? |
---|
[6b4d0b8] | 79 | * |
---|
[1362b7a] | 80 | * This feature conditional is used to indicate whether or not there |
---|
| 81 | * is software implemented floating point that must be context |
---|
| 82 | * switched. The determination of whether or not this applies |
---|
| 83 | * is very tool specific and the state saved/restored is also |
---|
| 84 | * compiler specific. |
---|
[6b4d0b8] | 85 | * |
---|
[1362b7a] | 86 | * Port Specific Information: |
---|
[6b4d0b8] | 87 | * |
---|
[1362b7a] | 88 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 89 | */ |
---|
| 90 | #define CPU_HARDWARE_FP FALSE |
---|
| 91 | #define CPU_SOFTWARE_FP FALSE |
---|
| 92 | |
---|
| 93 | /** |
---|
[1362b7a] | 94 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
---|
[6b4d0b8] | 95 | * |
---|
[1362b7a] | 96 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
---|
| 97 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
---|
[6b4d0b8] | 98 | * |
---|
[1362b7a] | 99 | * So far, the only CPUs in which this option has been used are the |
---|
| 100 | * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and |
---|
| 101 | * gcc both implicitly used the floating point registers to perform |
---|
| 102 | * integer multiplies. Similarly, the PowerPC port of gcc has been |
---|
| 103 | * seen to allocate floating point local variables and touch the FPU |
---|
| 104 | * even when the flow through a subroutine (like vfprintf()) might |
---|
| 105 | * not use floating point formats. |
---|
[6b4d0b8] | 106 | * |
---|
[1362b7a] | 107 | * If a function which you would not think utilize the FP unit DOES, |
---|
| 108 | * then one can not easily predict which tasks will use the FP hardware. |
---|
| 109 | * In this case, this option should be TRUE. |
---|
[6b4d0b8] | 110 | * |
---|
[1362b7a] | 111 | * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
---|
[6b4d0b8] | 112 | * |
---|
[1362b7a] | 113 | * Port Specific Information: |
---|
[6b4d0b8] | 114 | * |
---|
[1362b7a] | 115 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 116 | */ |
---|
| 117 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
| 118 | |
---|
| 119 | /** |
---|
[1362b7a] | 120 | * Should the IDLE task have a floating point context? |
---|
[6b4d0b8] | 121 | * |
---|
[1362b7a] | 122 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
---|
| 123 | * and it has a floating point context which is switched in and out. |
---|
| 124 | * If FALSE, then the IDLE task does not have a floating point context. |
---|
[6b4d0b8] | 125 | * |
---|
[1362b7a] | 126 | * Setting this to TRUE negatively impacts the time required to preempt |
---|
| 127 | * the IDLE task from an interrupt because the floating point context |
---|
| 128 | * must be saved as part of the preemption. |
---|
[6b4d0b8] | 129 | * |
---|
[1362b7a] | 130 | * Port Specific Information: |
---|
[6b4d0b8] | 131 | * |
---|
[1362b7a] | 132 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 133 | */ |
---|
| 134 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
| 135 | |
---|
| 136 | /** |
---|
[1362b7a] | 137 | * Should the saving of the floating point registers be deferred |
---|
| 138 | * until a context switch is made to another different floating point |
---|
| 139 | * task? |
---|
[6b4d0b8] | 140 | * |
---|
[1362b7a] | 141 | * If TRUE, then the floating point context will not be stored until |
---|
| 142 | * necessary. It will remain in the floating point registers and not |
---|
| 143 | * disturned until another floating point task is switched to. |
---|
[6b4d0b8] | 144 | * |
---|
[1362b7a] | 145 | * If FALSE, then the floating point context is saved when a floating |
---|
| 146 | * point task is switched out and restored when the next floating point |
---|
| 147 | * task is restored. The state of the floating point registers between |
---|
| 148 | * those two operations is not specified. |
---|
[6b4d0b8] | 149 | * |
---|
[1362b7a] | 150 | * If the floating point context does NOT have to be saved as part of |
---|
| 151 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
[6b4d0b8] | 152 | * |
---|
[1362b7a] | 153 | * Setting this flag to TRUE results in using a different algorithm |
---|
| 154 | * for deciding when to save and restore the floating point context. |
---|
| 155 | * The deferred FP switch algorithm minimizes the number of times |
---|
| 156 | * the FP context is saved and restored. The FP context is not saved |
---|
| 157 | * until a context switch is made to another, different FP task. |
---|
| 158 | * Thus in a system with only one FP task, the FP context will never |
---|
| 159 | * be saved or restored. |
---|
[6b4d0b8] | 160 | * |
---|
[1362b7a] | 161 | * Port Specific Information: |
---|
[6b4d0b8] | 162 | * |
---|
[1362b7a] | 163 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 164 | */ |
---|
| 165 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
| 166 | |
---|
[84e6f15] | 167 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
---|
| 168 | |
---|
[6b4d0b8] | 169 | /** |
---|
[1362b7a] | 170 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
[6b4d0b8] | 171 | * |
---|
[1362b7a] | 172 | * If TRUE, then the routine @ref _CPU_Thread_Idle_body |
---|
| 173 | * must be provided and is the default IDLE thread body instead of |
---|
| 174 | * @ref _CPU_Thread_Idle_body. |
---|
[6b4d0b8] | 175 | * |
---|
[1362b7a] | 176 | * If FALSE, then use the generic IDLE thread body if the BSP does |
---|
| 177 | * not provide one. |
---|
[6b4d0b8] | 178 | * |
---|
[1362b7a] | 179 | * This is intended to allow for supporting processors which have |
---|
| 180 | * a low power or idle mode. When the IDLE thread is executed, then |
---|
| 181 | * the CPU can be powered down. |
---|
[6b4d0b8] | 182 | * |
---|
[1362b7a] | 183 | * The order of precedence for selecting the IDLE thread body is: |
---|
[6b4d0b8] | 184 | * |
---|
[1362b7a] | 185 | * -# BSP provided |
---|
| 186 | * -# CPU dependent (if provided) |
---|
| 187 | * -# generic (if no BSP and no CPU dependent) |
---|
[6b4d0b8] | 188 | * |
---|
[1362b7a] | 189 | * Port Specific Information: |
---|
[6b4d0b8] | 190 | * |
---|
[1362b7a] | 191 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 192 | */ |
---|
| 193 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
---|
| 194 | |
---|
| 195 | /** |
---|
[1362b7a] | 196 | * Does the stack grow up (toward higher addresses) or down |
---|
| 197 | * (toward lower addresses)? |
---|
[6b4d0b8] | 198 | * |
---|
[1362b7a] | 199 | * If TRUE, then the grows upward. |
---|
| 200 | * If FALSE, then the grows toward smaller addresses. |
---|
[6b4d0b8] | 201 | * |
---|
[1362b7a] | 202 | * Port Specific Information: |
---|
[6b4d0b8] | 203 | * |
---|
[1362b7a] | 204 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 205 | */ |
---|
| 206 | #define CPU_STACK_GROWS_UP FALSE |
---|
| 207 | |
---|
[a8865f8] | 208 | /* L2 cache lines are 32 bytes in Milkymist SoC */ |
---|
| 209 | #define CPU_CACHE_LINE_BYTES 32 |
---|
| 210 | |
---|
| 211 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
---|
[6b4d0b8] | 212 | |
---|
| 213 | /** |
---|
[1362b7a] | 214 | * @ingroup CPUInterrupt |
---|
| 215 | * The following defines the number of bits actually used in the |
---|
| 216 | * interrupt field of the task mode. How those bits map to the |
---|
| 217 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
---|
[6b4d0b8] | 218 | * |
---|
[1362b7a] | 219 | * Port Specific Information: |
---|
[6b4d0b8] | 220 | * |
---|
[1362b7a] | 221 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 222 | */ |
---|
| 223 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
---|
| 224 | |
---|
[decff899] | 225 | #define CPU_MAXIMUM_PROCESSORS 32 |
---|
| 226 | |
---|
[6b4d0b8] | 227 | /* |
---|
| 228 | * Processor defined structures required for cpukit/score. |
---|
| 229 | * |
---|
| 230 | * Port Specific Information: |
---|
| 231 | * |
---|
| 232 | * XXX document implementation including references if appropriate |
---|
| 233 | */ |
---|
| 234 | |
---|
| 235 | /* may need to put some structures here. */ |
---|
| 236 | |
---|
| 237 | /** |
---|
| 238 | * @defgroup CPUContext Processor Dependent Context Management |
---|
| 239 | * |
---|
[1362b7a] | 240 | * From the highest level viewpoint, there are 2 types of context to save. |
---|
[6b4d0b8] | 241 | * |
---|
[1362b7a] | 242 | * -# Interrupt registers to save |
---|
| 243 | * -# Task level registers to save |
---|
[6b4d0b8] | 244 | * |
---|
[1362b7a] | 245 | * Since RTEMS handles integer and floating point contexts separately, this |
---|
| 246 | * means we have the following 3 context items: |
---|
[6b4d0b8] | 247 | * |
---|
[1362b7a] | 248 | * -# task level context stuff:: Context_Control |
---|
| 249 | * -# floating point task stuff:: Context_Control_fp |
---|
| 250 | * -# special interrupt level context :: CPU_Interrupt_frame |
---|
[6b4d0b8] | 251 | * |
---|
[1362b7a] | 252 | * On some processors, it is cost-effective to save only the callee |
---|
| 253 | * preserved registers during a task context switch. This means |
---|
| 254 | * that the ISR code needs to save those registers which do not |
---|
| 255 | * persist across function calls. It is not mandatory to make this |
---|
| 256 | * distinctions between the caller/callee saves registers for the |
---|
| 257 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
| 258 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
| 259 | * choice. Save the same context on interrupt entry as for tasks in |
---|
| 260 | * this case. |
---|
[6b4d0b8] | 261 | * |
---|
[1362b7a] | 262 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
| 263 | * care should be used in designing the context area. |
---|
[6b4d0b8] | 264 | * |
---|
[1362b7a] | 265 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
| 266 | * structure will not be used or it simply consist of an array of a |
---|
| 267 | * fixed number of bytes. This is done when the floating point context |
---|
| 268 | * is dumped by a "FP save context" type instruction and the format |
---|
| 269 | * is not really defined by the CPU. In this case, there is no need |
---|
| 270 | * to figure out the exact format -- only the size. Of course, although |
---|
| 271 | * this is enough information for RTEMS, it is probably not enough for |
---|
| 272 | * a debugger such as gdb. But that is another problem. |
---|
[6b4d0b8] | 273 | * |
---|
[1362b7a] | 274 | * Port Specific Information: |
---|
[6b4d0b8] | 275 | * |
---|
[1362b7a] | 276 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 277 | */ |
---|
[b697bc6] | 278 | /**@{**/ |
---|
[6b4d0b8] | 279 | |
---|
| 280 | /** |
---|
[1362b7a] | 281 | * This defines the minimal set of integer and processor state registers |
---|
| 282 | * that must be saved during a voluntary context switch from one thread |
---|
| 283 | * to another. |
---|
[6b4d0b8] | 284 | */ |
---|
| 285 | typedef struct { |
---|
| 286 | uint32_t r11; |
---|
| 287 | uint32_t r12; |
---|
| 288 | uint32_t r13; |
---|
| 289 | uint32_t r14; |
---|
| 290 | uint32_t r15; |
---|
| 291 | uint32_t r16; |
---|
| 292 | uint32_t r17; |
---|
| 293 | uint32_t r18; |
---|
| 294 | uint32_t r19; |
---|
| 295 | uint32_t r20; |
---|
| 296 | uint32_t r21; |
---|
| 297 | uint32_t r22; |
---|
| 298 | uint32_t r23; |
---|
| 299 | uint32_t r24; |
---|
| 300 | uint32_t r25; |
---|
| 301 | uint32_t gp; |
---|
| 302 | uint32_t fp; |
---|
| 303 | uint32_t sp; |
---|
| 304 | uint32_t ra; |
---|
[7c4c284c] | 305 | uint32_t ie; |
---|
[af2b90d] | 306 | uint32_t epc; |
---|
[6b4d0b8] | 307 | } Context_Control; |
---|
| 308 | |
---|
| 309 | /** |
---|
| 310 | * |
---|
[1362b7a] | 311 | * This macro returns the stack pointer associated with @a _context. |
---|
[6b4d0b8] | 312 | * |
---|
[1362b7a] | 313 | * @param[in] _context is the thread context area to access |
---|
[42e243e] | 314 | * |
---|
[1362b7a] | 315 | * @return This method returns the stack pointer. |
---|
[6b4d0b8] | 316 | */ |
---|
| 317 | #define _CPU_Context_Get_SP( _context ) \ |
---|
| 318 | (_context)->sp |
---|
| 319 | |
---|
| 320 | /** |
---|
[1362b7a] | 321 | * This defines the complete set of floating point registers that must |
---|
| 322 | * be saved during any context switch from one thread to another. |
---|
[6b4d0b8] | 323 | */ |
---|
| 324 | typedef struct { |
---|
| 325 | } Context_Control_fp; |
---|
| 326 | |
---|
| 327 | /** |
---|
[1362b7a] | 328 | * This defines the set of integer and processor state registers that must |
---|
| 329 | * be saved during an interrupt. This set does not include any which are |
---|
| 330 | * in @ref Context_Control. |
---|
[6b4d0b8] | 331 | */ |
---|
| 332 | typedef struct { |
---|
| 333 | uint32_t r1; |
---|
| 334 | uint32_t r2; |
---|
| 335 | uint32_t r3; |
---|
| 336 | uint32_t r4; |
---|
| 337 | uint32_t r5; |
---|
| 338 | uint32_t r6; |
---|
| 339 | uint32_t r7; |
---|
| 340 | uint32_t r8; |
---|
[7c4c284c] | 341 | uint32_t r9; |
---|
| 342 | uint32_t r10; |
---|
[6b4d0b8] | 343 | uint32_t ra; |
---|
| 344 | uint32_t ba; |
---|
[7c4c284c] | 345 | uint32_t ea; |
---|
[6b4d0b8] | 346 | } CPU_Interrupt_frame; |
---|
| 347 | |
---|
| 348 | /** |
---|
[1362b7a] | 349 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 350 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 351 | * @ref _CPU_Initialize and copied into the task's FP context area during |
---|
| 352 | * @ref _CPU_Context_Initialize. |
---|
[6b4d0b8] | 353 | * |
---|
[1362b7a] | 354 | * Port Specific Information: |
---|
[6b4d0b8] | 355 | * |
---|
[1362b7a] | 356 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 357 | */ |
---|
| 358 | #if 0 |
---|
[c6009340] | 359 | extern Context_Control_fp _CPU_Null_fp_context; |
---|
[6b4d0b8] | 360 | #endif |
---|
| 361 | |
---|
[1362b7a] | 362 | /** @} */ |
---|
| 363 | |
---|
[6b4d0b8] | 364 | /** |
---|
[1362b7a] | 365 | * @defgroup CPUInterrupt Processor Dependent Interrupt Management |
---|
[6b4d0b8] | 366 | */ |
---|
[b697bc6] | 367 | /**@{**/ |
---|
[6b4d0b8] | 368 | |
---|
| 369 | /* |
---|
[1362b7a] | 370 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
[6b4d0b8] | 371 | * |
---|
[1362b7a] | 372 | * Port Specific Information: |
---|
[6b4d0b8] | 373 | * |
---|
[1362b7a] | 374 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 375 | */ |
---|
| 376 | |
---|
| 377 | /* XXX: if needed, put more variables here */ |
---|
| 378 | |
---|
| 379 | /** |
---|
[1362b7a] | 380 | * @ingroup CPUContext |
---|
| 381 | * The size of the floating point context area. On some CPUs this |
---|
| 382 | * will not be a "sizeof" because the format of the floating point |
---|
| 383 | * area is not defined -- only the size is. This is usually on |
---|
| 384 | * CPUs with a "floating point save context" instruction. |
---|
[6b4d0b8] | 385 | * |
---|
[1362b7a] | 386 | * Port Specific Information: |
---|
[6b4d0b8] | 387 | * |
---|
[1362b7a] | 388 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 389 | */ |
---|
| 390 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 391 | |
---|
| 392 | /** |
---|
[1362b7a] | 393 | * Amount of extra stack (above minimum stack size) required by |
---|
| 394 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 395 | * system this thread must exist and be able to process all directives. |
---|
[6b4d0b8] | 396 | * |
---|
[1362b7a] | 397 | * Port Specific Information: |
---|
[6b4d0b8] | 398 | * |
---|
[1362b7a] | 399 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 400 | */ |
---|
| 401 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 402 | |
---|
| 403 | /** |
---|
[1362b7a] | 404 | * This defines the number of entries in the @ref _ISR_Vector_table managed |
---|
| 405 | * by RTEMS. |
---|
[6b4d0b8] | 406 | * |
---|
[1362b7a] | 407 | * Port Specific Information: |
---|
[6b4d0b8] | 408 | * |
---|
[1362b7a] | 409 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 410 | */ |
---|
| 411 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
---|
| 412 | |
---|
| 413 | /** |
---|
[1362b7a] | 414 | * This defines the highest interrupt vector number for this port. |
---|
[6b4d0b8] | 415 | */ |
---|
| 416 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
| 417 | |
---|
| 418 | /** |
---|
[1362b7a] | 419 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 420 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
---|
[6b4d0b8] | 421 | */ |
---|
| 422 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 423 | |
---|
[1362b7a] | 424 | /** @} */ |
---|
| 425 | |
---|
[6b4d0b8] | 426 | /** |
---|
[1362b7a] | 427 | * @ingroup CPUContext |
---|
| 428 | * Should be large enough to run all RTEMS tests. This ensures |
---|
| 429 | * that a "reasonable" small application should not have any problems. |
---|
[6b4d0b8] | 430 | * |
---|
[1362b7a] | 431 | * Port Specific Information: |
---|
[6b4d0b8] | 432 | * |
---|
[1362b7a] | 433 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 434 | */ |
---|
| 435 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
| 436 | |
---|
[f1738ed] | 437 | #define CPU_SIZEOF_POINTER 4 |
---|
| 438 | |
---|
[6b4d0b8] | 439 | /** |
---|
[1362b7a] | 440 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 441 | * alignment does not take into account the requirements for the stack. |
---|
[6b4d0b8] | 442 | * |
---|
[1362b7a] | 443 | * Port Specific Information: |
---|
| 444 | * The LM32 architecture manual simply states: "All memory accesses must be |
---|
| 445 | * aligned to the size of the access", and there is no hardware support |
---|
| 446 | * whatsoever for 64-bit numbers. |
---|
| 447 | * (lm32_archman.pdf, July 2009, p. 15) |
---|
[6b4d0b8] | 448 | */ |
---|
[7e8ed4d] | 449 | #define CPU_ALIGNMENT 4 |
---|
[6b4d0b8] | 450 | |
---|
| 451 | /** |
---|
[1362b7a] | 452 | * This number corresponds to the byte alignment requirement for the |
---|
| 453 | * heap handler. This alignment requirement may be stricter than that |
---|
| 454 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
---|
| 455 | * common for the heap to follow the same alignment requirement as |
---|
| 456 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
---|
| 457 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
---|
[6b4d0b8] | 458 | * |
---|
[1362b7a] | 459 | * NOTE: This does not have to be a power of 2 although it should be |
---|
| 460 | * a multiple of 2 greater than or equal to 2. The requirement |
---|
| 461 | * to be a multiple of 2 is because the heap uses the least |
---|
| 462 | * significant field of the front and back flags to indicate |
---|
| 463 | * that a block is in use or free. So you do not want any odd |
---|
| 464 | * length blocks really putting length data in that bit. |
---|
[6b4d0b8] | 465 | * |
---|
[1362b7a] | 466 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
---|
| 467 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
---|
| 468 | * elements allocated from the heap meet all restrictions. |
---|
[6b4d0b8] | 469 | * |
---|
[1362b7a] | 470 | * Port Specific Information: |
---|
[6b4d0b8] | 471 | * |
---|
[1362b7a] | 472 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 473 | */ |
---|
| 474 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 475 | |
---|
| 476 | /** |
---|
[1362b7a] | 477 | * This number corresponds to the byte alignment requirement for memory |
---|
| 478 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 479 | * may be stricter than that for the data types alignment specified by |
---|
| 480 | * @ref CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 481 | * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is |
---|
| 482 | * strict enough for the partition, then this should be set to |
---|
| 483 | * @ref CPU_ALIGNMENT. |
---|
[6b4d0b8] | 484 | * |
---|
[1362b7a] | 485 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 486 | * be greater or equal to than @ref CPU_ALIGNMENT. |
---|
[6b4d0b8] | 487 | * |
---|
[1362b7a] | 488 | * Port Specific Information: |
---|
[6b4d0b8] | 489 | * |
---|
[1362b7a] | 490 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 491 | */ |
---|
| 492 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 493 | |
---|
| 494 | /** |
---|
[1362b7a] | 495 | * This number corresponds to the byte alignment requirement for the |
---|
| 496 | * stack. This alignment requirement may be stricter than that for the |
---|
| 497 | * data types alignment specified by @ref CPU_ALIGNMENT. |
---|
[6b4d0b8] | 498 | * |
---|
| 499 | * |
---|
[1362b7a] | 500 | * Port Specific Information: |
---|
[6b4d0b8] | 501 | * |
---|
[1362b7a] | 502 | * Stack is software-managed |
---|
[6b4d0b8] | 503 | */ |
---|
[7e8ed4d] | 504 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
---|
[6b4d0b8] | 505 | |
---|
[c8df844] | 506 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
---|
| 507 | |
---|
[6b4d0b8] | 508 | /* |
---|
| 509 | * ISR handler macros |
---|
| 510 | */ |
---|
| 511 | |
---|
| 512 | /** |
---|
[1362b7a] | 513 | * @addtogroup CPUInterrupt |
---|
| 514 | */ |
---|
[b697bc6] | 515 | /**@{**/ |
---|
[1362b7a] | 516 | |
---|
| 517 | /** |
---|
| 518 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
[6b4d0b8] | 519 | * |
---|
[1362b7a] | 520 | * Port Specific Information: |
---|
| 521 | * |
---|
| 522 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 523 | */ |
---|
| 524 | #define _CPU_Initialize_vectors() |
---|
| 525 | |
---|
| 526 | /** |
---|
[1362b7a] | 527 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 528 | * level is returned in @a _isr_cookie. |
---|
[6b4d0b8] | 529 | * |
---|
[1362b7a] | 530 | * @param[out] _isr_cookie will contain the previous level cookie |
---|
[6b4d0b8] | 531 | * |
---|
[1362b7a] | 532 | * Port Specific Information: |
---|
[6b4d0b8] | 533 | * |
---|
[1362b7a] | 534 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 535 | */ |
---|
| 536 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 537 | lm32_disable_interrupts( _isr_cookie ); |
---|
| 538 | |
---|
| 539 | /** |
---|
[1362b7a] | 540 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 541 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 542 | * @a _isr_cookie is not modified. |
---|
[6b4d0b8] | 543 | * |
---|
[1362b7a] | 544 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[6b4d0b8] | 545 | * |
---|
[1362b7a] | 546 | * Port Specific Information: |
---|
[6b4d0b8] | 547 | * |
---|
[1362b7a] | 548 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 549 | */ |
---|
| 550 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 551 | lm32_enable_interrupts( _isr_cookie ); |
---|
| 552 | |
---|
| 553 | /** |
---|
[1362b7a] | 554 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
---|
| 555 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 556 | * sections into two or more parts. The parameter @a _isr_cookie is not |
---|
| 557 | * modified. |
---|
[6b4d0b8] | 558 | * |
---|
[1362b7a] | 559 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[6b4d0b8] | 560 | * |
---|
[1362b7a] | 561 | * Port Specific Information: |
---|
[6b4d0b8] | 562 | * |
---|
[1362b7a] | 563 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 564 | */ |
---|
| 565 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 566 | lm32_flash_interrupts( _isr_cookie ); |
---|
| 567 | |
---|
[408609f6] | 568 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
| 569 | { |
---|
| 570 | return ( level & 0x0001 ) != 0; |
---|
| 571 | } |
---|
| 572 | |
---|
[6b4d0b8] | 573 | /** |
---|
[1362b7a] | 574 | * This routine and @ref _CPU_ISR_Get_level |
---|
| 575 | * Map the interrupt level in task mode onto the hardware that the CPU |
---|
| 576 | * actually provides. Currently, interrupt levels which do not |
---|
| 577 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 578 | * it would be nice if these were "mapped" by the application |
---|
| 579 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 580 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 581 | * This could be used to manage a programmable interrupt controller |
---|
| 582 | * via the rtems_task_mode directive. |
---|
[6b4d0b8] | 583 | * |
---|
[1362b7a] | 584 | * Port Specific Information: |
---|
[6b4d0b8] | 585 | * |
---|
[1362b7a] | 586 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 587 | */ |
---|
| 588 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 589 | { \ |
---|
| 590 | _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | /** |
---|
[1362b7a] | 594 | * Return the current interrupt disable level for this task in |
---|
| 595 | * the format used by the interrupt level portion of the task mode. |
---|
[6b4d0b8] | 596 | * |
---|
[1362b7a] | 597 | * NOTE: This routine usually must be implemented as a subroutine. |
---|
[6b4d0b8] | 598 | * |
---|
[1362b7a] | 599 | * Port Specific Information: |
---|
[6b4d0b8] | 600 | * |
---|
[1362b7a] | 601 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 602 | */ |
---|
| 603 | uint32_t _CPU_ISR_Get_level( void ); |
---|
| 604 | |
---|
| 605 | /* end of ISR handler macros */ |
---|
| 606 | |
---|
[1362b7a] | 607 | /** @} */ |
---|
| 608 | |
---|
[6b4d0b8] | 609 | /* Context handler macros */ |
---|
| 610 | |
---|
| 611 | /** |
---|
[1362b7a] | 612 | * @ingroup CPUContext |
---|
| 613 | * Initialize the context to a state suitable for starting a |
---|
| 614 | * task after a context restore operation. Generally, this |
---|
| 615 | * involves: |
---|
[6b4d0b8] | 616 | * |
---|
[1362b7a] | 617 | * - setting a starting address |
---|
| 618 | * - preparing the stack |
---|
| 619 | * - preparing the stack and frame pointers |
---|
| 620 | * - setting the proper interrupt level in the context |
---|
| 621 | * - initializing the floating point context |
---|
[6b4d0b8] | 622 | * |
---|
[1362b7a] | 623 | * This routine generally does not set any unnecessary register |
---|
| 624 | * in the context. The state of the "general data" registers is |
---|
| 625 | * undefined at task start time. |
---|
| 626 | * |
---|
| 627 | * @param[in] _the_context is the context structure to be initialized |
---|
| 628 | * @param[in] _stack_base is the lowest physical address of this task's stack |
---|
| 629 | * @param[in] _size is the size of this task's stack |
---|
| 630 | * @param[in] _isr is the interrupt disable level |
---|
| 631 | * @param[in] _entry_point is the thread's entry point. This is |
---|
| 632 | * always @a _Thread_Handler |
---|
| 633 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
---|
| 634 | * point thread. This is typically only used on CPUs where the |
---|
| 635 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 636 | * where the PSR contains an enable FPU bit. |
---|
| 637 | * |
---|
| 638 | * Port Specific Information: |
---|
| 639 | * |
---|
| 640 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 641 | */ |
---|
[6d521f0] | 642 | extern char _gp[]; |
---|
| 643 | |
---|
[6b4d0b8] | 644 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
[022851a] | 645 | _isr, _entry_point, _is_fp, _tls_area ) \ |
---|
[6b4d0b8] | 646 | do { \ |
---|
| 647 | uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ |
---|
[a9c45a04] | 648 | \ |
---|
| 649 | (void) _is_fp; /* avoid warning for being unused */ \ |
---|
| 650 | (void) _isr; /* avoid warning for being unused */ \ |
---|
[524055a9] | 651 | (_the_context)->gp = (uint32_t)_gp; \ |
---|
| 652 | (_the_context)->fp = (uint32_t)_stack; \ |
---|
| 653 | (_the_context)->sp = (uint32_t)_stack; \ |
---|
| 654 | (_the_context)->ra = (uint32_t)(_entry_point); \ |
---|
[6b4d0b8] | 655 | } while ( 0 ) |
---|
| 656 | |
---|
| 657 | /** |
---|
[1362b7a] | 658 | * This routine is responsible for somehow restarting the currently |
---|
| 659 | * executing task. If you are lucky, then all that is necessary |
---|
| 660 | * is restoring the context. Otherwise, there will need to be |
---|
| 661 | * a special assembly routine which does something special in this |
---|
| 662 | * case. For many ports, simply adding a label to the restore path |
---|
| 663 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
---|
| 664 | * possibly to load a few arguments and jump to the restore path. It will |
---|
| 665 | * not work if restarting self conflicts with the stack frame |
---|
| 666 | * assumptions of restoring a context. |
---|
[6b4d0b8] | 667 | * |
---|
[1362b7a] | 668 | * Port Specific Information: |
---|
[6b4d0b8] | 669 | * |
---|
[1362b7a] | 670 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 671 | */ |
---|
| 672 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 673 | _CPU_Context_restore( (_the_context) ); |
---|
| 674 | |
---|
| 675 | /** |
---|
[1362b7a] | 676 | * This routine initializes the FP context area passed to it to. |
---|
| 677 | * There are a few standard ways in which to initialize the |
---|
| 678 | * floating point context. The code included for this macro assumes |
---|
| 679 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 680 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 681 | * context passed to it. |
---|
[6b4d0b8] | 682 | * |
---|
[1362b7a] | 683 | * Other floating point context save/restore models include: |
---|
| 684 | * -# not doing anything, and |
---|
| 685 | * -# putting a "null FP status word" in the correct place in the FP context. |
---|
[6b4d0b8] | 686 | * |
---|
[1362b7a] | 687 | * @param[in] _destination is the floating point context area |
---|
[6b4d0b8] | 688 | * |
---|
[1362b7a] | 689 | * Port Specific Information: |
---|
[6b4d0b8] | 690 | * |
---|
[1362b7a] | 691 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 692 | */ |
---|
| 693 | #define _CPU_Context_Initialize_fp( _destination ) |
---|
| 694 | #if 0 |
---|
| 695 | { \ |
---|
| 696 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
| 697 | } |
---|
| 698 | #endif |
---|
| 699 | |
---|
| 700 | /* end of Context handler macros */ |
---|
| 701 | |
---|
| 702 | /* Fatal Error manager macros */ |
---|
| 703 | |
---|
| 704 | /** |
---|
[1362b7a] | 705 | * This routine copies _error into a known place -- typically a stack |
---|
| 706 | * location or a register, optionally disables interrupts, and |
---|
| 707 | * halts/stops the CPU. |
---|
[6b4d0b8] | 708 | * |
---|
[1362b7a] | 709 | * Port Specific Information: |
---|
[6b4d0b8] | 710 | * |
---|
[1362b7a] | 711 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 712 | */ |
---|
[f82752a4] | 713 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
[6b4d0b8] | 714 | { \ |
---|
| 715 | } |
---|
| 716 | |
---|
| 717 | /* end of Fatal Error manager macros */ |
---|
| 718 | |
---|
| 719 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 720 | |
---|
| 721 | /* functions */ |
---|
| 722 | |
---|
| 723 | /** |
---|
[1362b7a] | 724 | * This routine performs CPU dependent initialization. |
---|
[6b4d0b8] | 725 | * |
---|
[1362b7a] | 726 | * Port Specific Information: |
---|
[6b4d0b8] | 727 | * |
---|
[1362b7a] | 728 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 729 | */ |
---|
[c03e2bc] | 730 | void _CPU_Initialize(void); |
---|
[6b4d0b8] | 731 | |
---|
| 732 | /** |
---|
[1362b7a] | 733 | * @addtogroup CPUInterrupt |
---|
| 734 | */ |
---|
[b697bc6] | 735 | /**@{**/ |
---|
[1362b7a] | 736 | |
---|
| 737 | /** |
---|
| 738 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 739 | * processor's vector table. |
---|
[6b4d0b8] | 740 | * |
---|
[1362b7a] | 741 | * @param[in] vector is the vector number |
---|
| 742 | * @param[in] new_handler is the raw ISR handler to install |
---|
| 743 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[6b4d0b8] | 744 | * |
---|
[1362b7a] | 745 | * Port Specific Information: |
---|
| 746 | * |
---|
| 747 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 748 | */ |
---|
| 749 | void _CPU_ISR_install_raw_handler( |
---|
| 750 | uint32_t vector, |
---|
| 751 | proc_ptr new_handler, |
---|
| 752 | proc_ptr *old_handler |
---|
| 753 | ); |
---|
| 754 | |
---|
| 755 | /** |
---|
[1362b7a] | 756 | * This routine installs an interrupt vector. |
---|
[6b4d0b8] | 757 | * |
---|
[1362b7a] | 758 | * @param[in] vector is the vector number |
---|
| 759 | * @param[in] new_handler is the RTEMS ISR handler to install |
---|
| 760 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[6b4d0b8] | 761 | * |
---|
[1362b7a] | 762 | * Port Specific Information: |
---|
[6b4d0b8] | 763 | * |
---|
[1362b7a] | 764 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 765 | */ |
---|
| 766 | void _CPU_ISR_install_vector( |
---|
| 767 | uint32_t vector, |
---|
| 768 | proc_ptr new_handler, |
---|
| 769 | proc_ptr *old_handler |
---|
| 770 | ); |
---|
| 771 | |
---|
[1362b7a] | 772 | /** @} */ |
---|
| 773 | |
---|
[6b4d0b8] | 774 | /** |
---|
[1362b7a] | 775 | * This routine is the CPU dependent IDLE thread body. |
---|
[6b4d0b8] | 776 | * |
---|
[1362b7a] | 777 | * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 778 | * is TRUE. |
---|
[6b4d0b8] | 779 | * |
---|
[1362b7a] | 780 | * Port Specific Information: |
---|
[6b4d0b8] | 781 | * |
---|
[1362b7a] | 782 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 783 | */ |
---|
[cca8379] | 784 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
[6b4d0b8] | 785 | |
---|
| 786 | /** |
---|
[1362b7a] | 787 | * @ingroup CPUContext |
---|
| 788 | * This routine switches from the run context to the heir context. |
---|
[6b4d0b8] | 789 | * |
---|
[1362b7a] | 790 | * @param[in] run points to the context of the currently executing task |
---|
| 791 | * @param[in] heir points to the context of the heir task |
---|
[6b4d0b8] | 792 | * |
---|
[1362b7a] | 793 | * Port Specific Information: |
---|
[6b4d0b8] | 794 | * |
---|
[1362b7a] | 795 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 796 | */ |
---|
| 797 | void _CPU_Context_switch( |
---|
| 798 | Context_Control *run, |
---|
| 799 | Context_Control *heir |
---|
| 800 | ); |
---|
| 801 | |
---|
| 802 | /** |
---|
[1362b7a] | 803 | * @addtogroup CPUContext |
---|
| 804 | */ |
---|
[b697bc6] | 805 | /**@{**/ |
---|
[1362b7a] | 806 | |
---|
| 807 | /** |
---|
| 808 | * This routine is generally used only to restart self in an |
---|
| 809 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
---|
[6b4d0b8] | 810 | * |
---|
[1362b7a] | 811 | * @param[in] new_context points to the context to be restored. |
---|
[6b4d0b8] | 812 | * |
---|
[1362b7a] | 813 | * NOTE: May be unnecessary to reload some registers. |
---|
[6b4d0b8] | 814 | * |
---|
[1362b7a] | 815 | * Port Specific Information: |
---|
| 816 | * |
---|
| 817 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 818 | */ |
---|
| 819 | void _CPU_Context_restore( |
---|
| 820 | Context_Control *new_context |
---|
[143696a] | 821 | ) RTEMS_NO_RETURN; |
---|
[6b4d0b8] | 822 | |
---|
| 823 | /** |
---|
[1362b7a] | 824 | * This routine saves the floating point context passed to it. |
---|
[6b4d0b8] | 825 | * |
---|
[1362b7a] | 826 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
| 827 | * point context area |
---|
[6b4d0b8] | 828 | * |
---|
[1362b7a] | 829 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 830 | * should be used with @ref _CPU_Context_restore_fp to restore this context. |
---|
[6b4d0b8] | 831 | * |
---|
[1362b7a] | 832 | * Port Specific Information: |
---|
[6b4d0b8] | 833 | * |
---|
[1362b7a] | 834 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 835 | */ |
---|
| 836 | void _CPU_Context_save_fp( |
---|
| 837 | Context_Control_fp **fp_context_ptr |
---|
| 838 | ); |
---|
| 839 | |
---|
| 840 | /** |
---|
[1362b7a] | 841 | * This routine restores the floating point context passed to it. |
---|
[6b4d0b8] | 842 | * |
---|
[1362b7a] | 843 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
| 844 | * point context area to restore |
---|
[6b4d0b8] | 845 | * |
---|
[1362b7a] | 846 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 847 | * should be used with @ref _CPU_Context_save_fp to save this context. |
---|
[6b4d0b8] | 848 | * |
---|
[1362b7a] | 849 | * Port Specific Information: |
---|
[6b4d0b8] | 850 | * |
---|
[1362b7a] | 851 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 852 | */ |
---|
| 853 | void _CPU_Context_restore_fp( |
---|
| 854 | Context_Control_fp **fp_context_ptr |
---|
| 855 | ); |
---|
| 856 | |
---|
[1362b7a] | 857 | /** @} */ |
---|
| 858 | |
---|
[815994f] | 859 | /* FIXME */ |
---|
| 860 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
---|
| 861 | |
---|
| 862 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
| 863 | |
---|
[6b4d0b8] | 864 | /** |
---|
[1362b7a] | 865 | * @ingroup CPUEndian |
---|
| 866 | * The following routine swaps the endian format of an unsigned int. |
---|
| 867 | * It must be static because it is referenced indirectly. |
---|
[6b4d0b8] | 868 | * |
---|
[1362b7a] | 869 | * This version will work on any processor, but if there is a better |
---|
| 870 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
[6b4d0b8] | 871 | * |
---|
[1362b7a] | 872 | * swap least significant two bytes with 16-bit rotate |
---|
| 873 | * swap upper and lower 16-bits |
---|
| 874 | * swap most significant two bytes with 16-bit rotate |
---|
[6b4d0b8] | 875 | * |
---|
[1362b7a] | 876 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 877 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 878 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
| 879 | * that interrupts would probably have to be disabled to ensure that |
---|
| 880 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 881 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 882 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 883 | * will be fetched incorrectly. |
---|
[6b4d0b8] | 884 | * |
---|
[1362b7a] | 885 | * @param[in] value is the value to be swapped |
---|
| 886 | * @return the value after being endian swapped |
---|
[6b4d0b8] | 887 | * |
---|
[1362b7a] | 888 | * Port Specific Information: |
---|
[6b4d0b8] | 889 | * |
---|
[1362b7a] | 890 | * XXX document implementation including references if appropriate |
---|
[6b4d0b8] | 891 | */ |
---|
| 892 | static inline uint32_t CPU_swap_u32( |
---|
| 893 | uint32_t value |
---|
| 894 | ) |
---|
| 895 | { |
---|
| 896 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[42e243e] | 897 | |
---|
[6b4d0b8] | 898 | byte4 = (value >> 24) & 0xff; |
---|
| 899 | byte3 = (value >> 16) & 0xff; |
---|
| 900 | byte2 = (value >> 8) & 0xff; |
---|
| 901 | byte1 = value & 0xff; |
---|
[42e243e] | 902 | |
---|
[6b4d0b8] | 903 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 904 | return swapped; |
---|
| 905 | } |
---|
| 906 | |
---|
| 907 | /** |
---|
[1362b7a] | 908 | * @ingroup CPUEndian |
---|
| 909 | * This routine swaps a 16 bir quantity. |
---|
[6b4d0b8] | 910 | * |
---|
[1362b7a] | 911 | * @param[in] value is the value to be swapped |
---|
| 912 | * @return the value after being endian swapped |
---|
[6b4d0b8] | 913 | */ |
---|
[552a80fc] | 914 | static inline uint16_t CPU_swap_u16(uint16_t v) |
---|
| 915 | { |
---|
| 916 | return v << 8 | v >> 8; |
---|
| 917 | } |
---|
[6b4d0b8] | 918 | |
---|
[24bf11e] | 919 | typedef uint32_t CPU_Counter_ticks; |
---|
| 920 | |
---|
[65f868c] | 921 | uint32_t _CPU_Counter_frequency( void ); |
---|
| 922 | |
---|
[24bf11e] | 923 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
| 924 | |
---|
| 925 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 926 | CPU_Counter_ticks second, |
---|
| 927 | CPU_Counter_ticks first |
---|
| 928 | ) |
---|
| 929 | { |
---|
| 930 | return second - first; |
---|
| 931 | } |
---|
| 932 | |
---|
[c98d4748] | 933 | /** Type that can store a 32-bit integer or a pointer. */ |
---|
| 934 | typedef uintptr_t CPU_Uint32ptr; |
---|
| 935 | |
---|
[6b4d0b8] | 936 | #ifdef __cplusplus |
---|
| 937 | } |
---|
| 938 | #endif |
---|
| 939 | |
---|
| 940 | #endif |
---|