Changeset 7e8ed4d in rtems


Ignore:
Timestamp:
Nov 28, 2011, 5:36:35 PM (8 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, master
Children:
ece1759
Parents:
e5a8020
Message:

2011-11-28 Werner Almesberger <werner@…>

PR 1956/cpukit

  • rtems/score/cpu.h: Correct multiple alignment constants. Improve comments.
Location:
cpukit/score/cpu/lm32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/lm32/ChangeLog

    re5a8020 r7e8ed4d  
     12011-11-28      Werner Almesberger <werner@almesberger.net>
     2
     3        PR 1956/cpukit
     4        * rtems/score/cpu.h: Correct multiple alignment constants. Improve
     5        comments.
     6
    172011-11-09      Werner Almesberger <werner@almesberger.net>
    28
  • cpukit/score/cpu/lm32/rtems/score/cpu.h

    re5a8020 r7e8ed4d  
    44
    55/*
    6  *  This include file contains information pertaining to the XXX
     6 *  This include file contains information pertaining to the LM32
    77 *  processor.
    8  *
    9  *  @note This file is part of a porting template that is intended
    10  *  to be used as the starting point when porting RTEMS to a new
    11  *  CPU family.  The following needs to be done when using this as
    12  *  the starting point for a new port:
    13  *
    14  *  + Anywhere there is an XXX, it should be replaced
    15  *    with information about the CPU family being ported to.
    16  *
    17  *  + At the end of each comment section, there is a heading which
    18  *    says "Port Specific Information:".  When porting to RTEMS,
    19  *    add CPU family specific information in this section
    208 */
    219
     
    348336 *  Port Specific Information:
    349337 *
    350  *  XXX document implementation including references if appropriate
    351  */
    352 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8)))
     338 *  L2 cache lines are 32 bytes in Milkymist SoC
     339 */
     340#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
    353341
    354342#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
     
    635623 *
    636624 *  Port Specific Information:
    637  *
    638  *  XXX document implementation including references if appropriate
    639  */
    640 #define CPU_ALIGNMENT              8
     625 *  The LM32 architecture manual simply states: "All memory accesses must be
     626 *  aligned to the size of the access", and there is no hardware support
     627 *  whatsoever for 64-bit numbers.
     628 *  (lm32_archman.pdf, July 2009, p. 15)
     629 */
     630#define CPU_ALIGNMENT              4
    641631
    642632/**
     
    686676 *  This number corresponds to the byte alignment requirement for the
    687677 *  stack.  This alignment requirement may be stricter than that for the
    688  *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
    689  *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
    690  *  set to 0.
    691  *
    692  *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
    693  *
    694  *  Port Specific Information:
    695  *
    696  *  XXX document implementation including references if appropriate
    697  */
    698 #define CPU_STACK_ALIGNMENT        4
     678 *  data types alignment specified by @ref CPU_ALIGNMENT.
     679 *
     680 *
     681 *  Port Specific Information:
     682 *
     683 *  Stack is software-managed
     684 */
     685#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
    699686
    700687/*
Note: See TracChangeset for help on using the changeset viewer.