Changeset 022851a in rtems


Ignore:
Timestamp:
Jan 28, 2014, 11:10:08 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
1e744ef
Parents:
960fd85
git-author:
Sebastian Huber <sebastian.huber@…> (01/28/14 11:10:08)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/04/14 09:06:35)
Message:

Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.

Files:
17 added
60 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu.c

    r960fd85 r022851a  
    3535#include <rtems/score/interr.h>
    3636#include <rtems/score/cpu.h>
     37#include <rtems/score/tls.h>
    3738#include <rtems/powerpc/powerpc.h>
    3839
     
    6364  uint32_t          new_level,
    6465  void             *entry_point,
    65   bool              is_fp
     66  bool              is_fp,
     67  void             *tls_area
    6668)
    6769{
     
    6971  uint32_t   msr_value;
    7072  uint32_t   sp;
    71   register uint32_t gpr2 __asm__("2");
    7273
    7374  sp = (uint32_t)stack_base + size - PPC_MINIMUM_STACK_FRAME_SIZE;
     
    129130  the_ppc_context->msr = msr_value;
    130131  the_ppc_context->lr = (uint32_t) entry_point;
    131   the_ppc_context->gpr2 = gpr2;
    132132
    133133#ifdef __ALTIVEC__
    134134  _CPU_Context_initialize_altivec( the_ppc_context );
    135135#endif
     136
     137  if ( tls_area != NULL ) {
     138    void *tls_block = _TLS_TCB_before_tls_block_initialize( tls_area );
     139
     140    the_ppc_context->gpr2 = (uint32_t) tls_block + 0x7000;
     141  } else {
     142    register uint32_t gpr2 __asm__("2");
     143
     144    the_ppc_context->gpr2 = gpr2;
     145  }
    136146}
  • cpukit/score/Makefile.am

    r960fd85 r022851a  
    7575include_rtems_score_HEADERS += include/rtems/score/timestamp.h
    7676include_rtems_score_HEADERS += include/rtems/score/timestamp64.h
     77include_rtems_score_HEADERS += include/rtems/score/tls.h
    7778include_rtems_score_HEADERS += include/rtems/score/tod.h
    7879include_rtems_score_HEADERS += include/rtems/score/todimpl.h
  • cpukit/score/cpu/arm/Makefile.am

    r960fd85 r022851a  
    1616libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
    1717libscorecpu_a_SOURCES =
     18libscorecpu_a_SOURCES += __aeabi_read_tp.c
     19libscorecpu_a_SOURCES += __tls_get_addr.c
    1820libscorecpu_a_SOURCES += cpu.c
    1921libscorecpu_a_SOURCES += cpu_asm.S
  • cpukit/score/cpu/arm/armv7m-context-initialize.c

    r960fd85 r022851a  
    2727#include <rtems/score/armv7m.h>
    2828#include <rtems/score/thread.h>
     29#include <rtems/score/tls.h>
    2930
    3031#ifdef ARM_MULTILIB_ARCH_V7M
     
    3637  uint32_t new_level,
    3738  void (*entry_point)( void ),
    38   bool is_fp
     39  bool is_fp,
     40  void *tls_area
    3941)
    4042{
     
    4547  context->register_lr = entry_point;
    4648  context->register_sp = stack_area_end;
     49
     50  if ( tls_area != NULL ) {
     51    _TLS_TCB_at_area_begin_initialize( tls_area );
     52  }
    4753}
    4854
  • cpukit/score/cpu/arm/cpu.c

    r960fd85 r022851a  
    3333#include <rtems/score/wkspace.h>
    3434#include <rtems/score/thread.h>
     35#include <rtems/score/tls.h>
    3536#include <rtems/score/cpu.h>
    3637
     
    3940    offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET,
    4041    ARM_CONTEXT_CONTROL_D8_OFFSET
     42  );
     43#endif
     44
     45#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     46  RTEMS_STATIC_ASSERT(
     47    offsetof( Context_Control, thread_id )
     48      == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
     49    ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
    4150  );
    4251#endif
     
    7281  uint32_t new_level,
    7382  void (*entry_point)( void ),
    74   bool is_fp
     83  bool is_fp,
     84  void *tls_area
    7585)
    7686{
     
    7989  the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
    8090    | arm_cpu_mode;
     91
     92#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     93  the_context->thread_id = (uint32_t) tls_area;
     94#endif
     95
     96  if ( tls_area != NULL ) {
     97    _TLS_TCB_at_area_begin_initialize( tls_area );
     98  }
    8199}
    82100
  • cpukit/score/cpu/arm/cpu_asm.S

    r960fd85 r022851a  
    6363#endif
    6464
     65#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     66        mrc     p15, 0, r3, c13, c0, 3
     67        str     r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
     68#endif
     69
    6570/* Start restoring context */
    6671_restore:
    6772#ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
    6873        clrex
     74#endif
     75
     76#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     77        ldr     r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
     78        mcr     p15, 0, r3, c13, c0, 3
    6979#endif
    7080
  • cpukit/score/cpu/arm/rtems/score/arm.h

    r960fd85 r022851a  
    4545#endif
    4646
     47#if defined(__ARM_ARCH_7A__) \
     48  || defined(__ARM_ARCH_7R__)
     49  #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     50#endif
     51
    4752#if defined(__ARM_NEON__)
    4853  #define ARM_MULTILIB_VFP_D32
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r960fd85 r022851a  
    212212
    213213/** @} */
     214
     215#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     216  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
     217#endif
    214218
    215219#ifdef ARM_MULTILIB_VFP_D32
     
    268272  void *register_sp;
    269273#endif
     274#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     275  uint32_t thread_id;
     276#endif
    270277#ifdef ARM_MULTILIB_VFP_D32
    271278  uint64_t register_d8;
     
    401408  uint32_t new_level,
    402409  void (*entry_point)( void ),
    403   bool is_fp
     410  bool is_fp,
     411  void *tls_area
    404412);
    405413
  • cpukit/score/cpu/avr/rtems/score/cpu.h

    r960fd85 r022851a  
    964964  uint32_t          new_level,
    965965  void             *entry_point,
    966   bool              is_fp
     966  bool              is_fp,
     967  void             *tls_area
    967968);
    968969
  • cpukit/score/cpu/bfin/cpu.c

    r960fd85 r022851a  
    187187  uint32_t          new_level,
    188188  void             *entry_point,
    189   bool              is_fp
     189  bool              is_fp,
     190  void             *tls_area
    190191)
    191192{
  • cpukit/score/cpu/bfin/rtems/score/cpu.h

    r960fd85 r022851a  
    818818 *       FPU may be easily disabled by software such as on the SPARC
    819819 *       where the PSR contains an enable FPU bit.
     820 * @param[in] tls_area is the thread-local storage (TLS) area
    820821 *
    821822 * Port Specific Information:
     
    829830  uint32_t          new_level,
    830831  void             *entry_point,
    831   bool              is_fp
     832  bool              is_fp,
     833  void             *tls_area
    832834);
    833835
  • cpukit/score/cpu/h8300/rtems/score/cpu.h

    r960fd85 r022851a  
    757757
    758758#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    759                                    _isr, _entry_point, _is_fp ) \
     759                                   _isr, _entry_point, _is_fp, _tls_area ) \
    760760  /* Locate Me */ \
    761761  do { \
  • cpukit/score/cpu/i386/rtems/score/cpu.h

    r960fd85 r022851a  
    444444
    445445#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    446                                    _isr, _entry_point, _is_fp ) \
     446                                   _isr, _entry_point, _is_fp, _tls_area ) \
    447447  do { \
    448448    uint32_t   _stack; \
  • cpukit/score/cpu/lm32/rtems/score/cpu.h

    r960fd85 r022851a  
    824824
    825825#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    826                                  _isr, _entry_point, _is_fp ) \
     826                                 _isr, _entry_point, _is_fp, _tls_area ) \
    827827   do { \
    828828     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
  • cpukit/score/cpu/m32c/context_init.c

    r960fd85 r022851a  
    5151  uint32_t          new_level,
    5252  void             *entry_point,
    53   bool              is_fp
     53  bool              is_fp,
     54  void             *tls_area
    5455)
    5556{
  • cpukit/score/cpu/m32c/rtems/score/cpu.h

    r960fd85 r022851a  
    810810 *       FPU may be easily disabled by software such as on the SPARC
    811811 *       where the PSR contains an enable FPU bit.
     812 * @param[in] tls_area is the thread-local storage (TLS) area
    812813 *
    813814 * Port Specific Information:
     
    821822  uint32_t          new_level,
    822823  void             *entry_point,
    823   bool              is_fp
     824  bool              is_fp,
     825  void             *tls_area
    824826);
    825827
  • cpukit/score/cpu/m32r/context_init.c

    r960fd85 r022851a  
    3434  uint32_t          new_level,
    3535  void             *entry_point,
    36   bool              is_fp
     36  bool              is_fp,
     37  void             *tls_area
    3738)
    3839{
  • cpukit/score/cpu/m32r/rtems/score/cpu.h

    r960fd85 r022851a  
    829829 *       FPU may be easily disabled by software such as on the SPARC
    830830 *       where the PSR contains an enable FPU bit.
     831 * @param[in] tls_area is the thread-local storage (TLS) area
    831832 *
    832833 * Port Specific Information:
     
    840841  uint32_t          new_level,
    841842  void             *entry_point,
    842   bool              is_fp
     843  bool              is_fp,
     844  void             *tls_area
    843845);
    844846
  • cpukit/score/cpu/m68k/Makefile.am

    r960fd85 r022851a  
    2121libscorecpu_a_SOURCES = cpu.c cpu_asm.S
    2222libscorecpu_a_SOURCES += m68k-exception-frame-print.c
     23libscorecpu_a_SOURCES += __m68k_read_tp.c
    2324
    2425include $(srcdir)/preinstall.am
  • cpukit/score/cpu/m68k/cpu.c

    r960fd85 r022851a  
    2020#include <rtems/system.h>
    2121#include <rtems/score/isr.h>
     22#include <rtems/score/tls.h>
    2223
    2324#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
     
    182183}
    183184#endif
     185
     186void _CPU_Context_Initialize(
     187  Context_Control *the_context,
     188  void *stack_area_begin,
     189  size_t stack_area_size,
     190  uint32_t new_level,
     191  void (*entry_point)( void ),
     192  bool is_fp,
     193  void *tls_area
     194)
     195{
     196  uint32_t stack;
     197
     198  the_context->sr      = 0x3000 | (new_level << 8);
     199  stack                = (uint32_t)stack_area_begin + stack_area_size - 4;
     200  the_context->a7_msp  = (void *)stack;
     201  *(void **)stack      = (void *)entry_point;
     202
     203#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
     204  the_context->fpu_dis = is_fp ? 0x00 : 0x10;
     205#endif
     206
     207  if ( tls_area != NULL ) {
     208    _TLS_TCB_before_tls_block_initialize( tls_area );
     209  }
     210}
  • cpukit/score/cpu/m68k/rtems/score/cpu.h

    r960fd85 r022851a  
    449449 */
    450450
    451 #if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
    452 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    453                                  _isr, _entry_point, _is_fp ) \
    454    do { \
    455      uint32_t   _stack; \
    456      \
    457      (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
    458      _stack                  = (uint32_t)(_stack_base) + (_size) - 4; \
    459      (_the_context)->a7_msp  = (void *)_stack; \
    460      *(void **)_stack        = (void *)(_entry_point); \
    461      (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10;          \
    462    } while ( 0 )
    463 #else
    464 #define _CPU_Context_Initialize( _the_context, _stack_base, _size,      \
    465                                  _isr, _entry_point, _is_fp )           \
    466    do {                                                                 \
    467      uint32_t   _stack;                                                 \
    468                                                                         \
    469      (_the_context)->sr      = 0x3000 | ((_isr) << 8);                  \
    470      _stack                  = (uint32_t)(_stack_base) + (_size) - 4;   \
    471      (_the_context)->a7_msp  = (void *)_stack;                          \
    472      *(void **)_stack        = (void *)(_entry_point);                  \
    473    } while ( 0 )
    474 #endif
     451void _CPU_Context_Initialize(
     452  Context_Control *the_context,
     453  void *stack_area_begin,
     454  size_t stack_area_size,
     455  uint32_t new_level,
     456  void (*entry_point)( void ),
     457  bool is_fp,
     458  void *tls_area
     459);
    475460
    476461/* end of Context handler macros */
  • cpukit/score/cpu/mips/cpu.c

    r960fd85 r022851a  
    174174  uint32_t          new_level,
    175175  void             *entry_point,
    176   bool              is_fp
     176  bool              is_fp,
     177  void             *tls_area
    177178)
    178179{
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r960fd85 r022851a  
    859859  uint32_t          new_level,
    860860  void             *entry_point,
    861   bool              is_fp
     861  bool              is_fp,
     862  void             *tls_area
    862863);
    863864
  • cpukit/score/cpu/moxie/rtems/score/cpu.h

    r960fd85 r022851a  
    652652
    653653#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    654                                  _isr, _entry_point, _is_fp )      \
     654                                 _isr, _entry_point, _is_fp, _tls_area ) \
    655655  /* Locate Me */                                                  \
    656656  do {                                                             \
  • cpukit/score/cpu/nios2/nios2-context-initialize.c

    r960fd85 r022851a  
    2828  uint32_t new_level,
    2929  void (*entry_point)( void ),
    30   bool is_fp
     30  bool is_fp,
     31  void *tls_area
    3132)
    3233{
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r960fd85 r022851a  
    296296 * @param[in] entry_point is the task's entry point
    297297 * @param[in] is_fp is set to @c true if the task is a floating point task
     298 * @param[in] tls_area is the thread-local storage (TLS) area
    298299 */
    299300void _CPU_Context_Initialize(
     
    303304  uint32_t new_level,
    304305  void (*entry_point)( void ),
    305   bool is_fp
     306  bool is_fp,
     307  void *tls_area
    306308);
    307309
  • cpukit/score/cpu/no_cpu/rtems/score/cpu.h

    r960fd85 r022851a  
    933933 *       FPU may be easily disabled by software such as on the SPARC
    934934 *       where the PSR contains an enable FPU bit.
     935 * @param[in] _tls_area The thread-local storage (TLS) area.
    935936 *
    936937 * Port Specific Information:
     
    939940 */
    940941#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    941                                  _isr, _entry_point, _is_fp ) \
     942                                 _isr, _entry_point, _is_fp, _tls_area ) \
    942943  { \
    943944  }
  • cpukit/score/cpu/powerpc/rtems/score/cpu.h

    r960fd85 r022851a  
    798798  uint32_t          new_level,
    799799  void             *entry_point,
    800   bool              is_fp
     800  bool              is_fp,
     801  void             *tls_area
    801802);
    802803
  • cpukit/score/cpu/sh/cpu.c

    r960fd85 r022851a  
    212212  uint32_t              _isr,
    213213  void  (*_entry_point)(void),
    214   int                   _is_fp )
     214  int                   _is_fp,
     215  void                  *_tls_base)
    215216{
    216217  _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) );
  • cpukit/score/cpu/sh/rtems/score/cpu.h

    r960fd85 r022851a  
    604604  uint32_t              _isr,
    605605  void    (*_entry_point)(void),
    606   int                   _is_fp );
     606  int                   _is_fp,
     607  void                  *_tls_area );
    607608
    608609/*
  • cpukit/score/cpu/sparc/cpu.c

    r960fd85 r022851a  
    2121#include <rtems/score/isr.h>
    2222#include <rtems/score/percpu.h>
     23#include <rtems/score/tls.h>
    2324#include <rtems/rtems/cache.h>
    2425
     
    233234  uint32_t          new_level,
    234235  void             *entry_point,
    235   bool              is_fp
     236  bool              is_fp,
     237  void             *tls_area
    236238)
    237239{
     
    286288   */
    287289    the_context->isr_dispatch_disable = 0;
    288 }
     290
     291  if ( tls_area != NULL ) {
     292    void *tcb = _TLS_TCB_after_tls_block_initialize( tls_area );
     293
     294    the_context->g7 = (uintptr_t) tcb;
     295  }
     296}
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    r960fd85 r022851a  
    10201020 * @param[in] entry_point is the task's entry point
    10211021 * @param[in] is_fp is set to TRUE if the task is a floating point task
     1022 * @param[in] tls_area is the thread-local storage (TLS) area
    10221023 *
    10231024 * NOTE:  Implemented as a subroutine for the SPARC port.
     
    10291030  uint32_t          new_level,
    10301031  void             *entry_point,
    1031   bool              is_fp
     1032  bool              is_fp,
     1033  void             *tls_area
    10321034);
    10331035
  • cpukit/score/cpu/sparc64/cpu.c

    r960fd85 r022851a  
    2121#include <rtems/asm.h>
    2222#include <rtems/score/isr.h>
     23#include <rtems/score/tls.h>
    2324#include <rtems/rtems/cache.h>
    2425
     
    6667  uint32_t          new_level,
    6768  void             *entry_point,
    68   bool              is_fp
     69  bool              is_fp,
     70  void             *tls_area
    6971)
    7072{
     
    100102   */
    101103    the_context->isr_dispatch_disable = 0;
     104
     105  if ( tls_area != NULL ) {
     106    void *tcb = _TLS_TCB_after_tls_block_initialize( tls_area );
     107
     108    the_context->g7 = (uintptr_t) tcb;
     109  }
    102110}
  • cpukit/score/cpu/sparc64/rtems/score/cpu.h

    r960fd85 r022851a  
    839839  uint32_t          new_level,
    840840  void             *entry_point,
    841   bool              is_fp
     841  bool              is_fp,
     842  void             *tls_area
    842843);
    843844
  • cpukit/score/cpu/v850/cpu.c

    r960fd85 r022851a  
    6262  uint32_t          new_level,
    6363  void             *entry_point,
    64   bool              is_fp
     64  bool              is_fp,
     65  void             *tls_area
    6566)
    6667{
  • cpukit/score/cpu/v850/rtems/score/cpu.h

    r960fd85 r022851a  
    791791 *       FPU may be easily disabled by software such as on the SPARC
    792792 *       where the PSR contains an enable FPU bit.
     793 * @param[in] tls_area is the thread-local storage (TLS) area
    793794 *
    794795 * Port Specific Information:
     
    802803  uint32_t          new_level,
    803804  void             *entry_point,
    804   bool              is_fp
     805  bool              is_fp,
     806  void             *tls_area
    805807);
    806808
  • cpukit/score/include/rtems/score/context.h

    r960fd85 r022851a  
    6161 *  @param[in] _is_fp is set to true if this thread has floating point
    6262 *         enabled
     63 *  @param[in] _tls_area The thread-local storage (TLS) area begin.
    6364 */
    64 #define _Context_Initialize(_the_context, _stack, _size, _isr, _entry, _is_fp) \
    65    _CPU_Context_Initialize( _the_context, _stack, _size, _isr, _entry, _is_fp )
     65#define _Context_Initialize( _the_context, _stack, _size, _isr, _entry, \
     66  _is_fp, _tls_area ) \
     67    _CPU_Context_Initialize( _the_context, _stack, _size, _isr, _entry, \
     68      _is_fp, _tls_area )
    6669
    6770/**
  • cpukit/score/include/rtems/score/thread.h

    r960fd85 r022851a  
    230230  /** This field is the initial stack area address. */
    231231  void                                *stack;
     232  /** The thread-local storage (TLS) area */
     233  void                                *tls_area;
    232234} Thread_Start_information;
    233235
  • cpukit/score/preinstall.am

    r960fd85 r022851a  
    280280PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/timestamp64.h
    281281
     282$(PROJECT_INCLUDE)/rtems/score/tls.h: include/rtems/score/tls.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
     283        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/tls.h
     284PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/tls.h
     285
    282286$(PROJECT_INCLUDE)/rtems/score/tod.h: include/rtems/score/tod.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
    283287        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/tod.h
  • cpukit/score/src/threadclose.c

    r960fd85 r022851a  
    9797  _Workspace_Free( the_thread->extensions );
    9898  the_thread->extensions = NULL;
     99
     100  _Workspace_Free( the_thread->Start.tls_area );
    99101}
  • cpukit/score/src/threadinitialize.c

    r960fd85 r022851a  
    2121#include <rtems/score/schedulerimpl.h>
    2222#include <rtems/score/stackimpl.h>
     23#include <rtems/score/tls.h>
    2324#include <rtems/score/userextimpl.h>
    2425#include <rtems/score/watchdogimpl.h>
     
    4950  bool                 extension_status;
    5051  int                  i;
     52  uintptr_t            tls_size = (uintptr_t) _TLS_Size;
    5153
    5254#if defined( RTEMS_SMP )
     
    7173  extensions_area = NULL;
    7274  the_thread->libc_reent = NULL;
     75  the_thread->Start.tls_area = NULL;
    7376
    7477  #if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE )
     
    105108     actual_stack_size
    106109  );
     110
     111  /* Thread-local storage (TLS) area allocation */
     112  if ( tls_size > 0 ) {
     113    uintptr_t tls_align = _TLS_Heap_align_up( (uintptr_t) _TLS_Alignment );
     114    uintptr_t tls_alloc = _TLS_Get_allocation_size( tls_size, tls_align );
     115
     116    the_thread->Start.tls_area =
     117      _Workspace_Allocate_aligned( tls_alloc, tls_align );
     118
     119    if ( the_thread->Start.tls_area == NULL ) {
     120      goto failed;
     121    }
     122  }
    107123
    108124  /*
     
    224240
    225241failed:
     242  _Workspace_Free( the_thread->Start.tls_area );
     243
    226244  _Workspace_Free( the_thread->libc_reent );
    227245
  • cpukit/score/src/threadloadenv.c

    r960fd85 r022851a  
    5959    isr_level,
    6060    _Thread_Handler,
    61     is_fp
     61    is_fp,
     62    the_thread->Start.tls_area
    6263  );
    6364
  • cpukit/score/src/wkspace.c

    r960fd85 r022851a  
    2222#include <rtems/score/heapimpl.h>
    2323#include <rtems/score/interr.h>
     24#include <rtems/score/threadimpl.h>
     25#include <rtems/score/tls.h>
    2426#include <rtems/config.h>
    2527
     
    3032  #include <rtems/bspIo.h>
    3133#endif
     34
     35static uint32_t _Get_maximum_thread_count(void)
     36{
     37  uint32_t thread_count = 0;
     38
     39  thread_count += _Thread_Get_maximum_internal_threads();
     40
     41  thread_count += rtems_resource_maximum_per_allocation(
     42    Configuration_RTEMS_API.maximum_tasks
     43  );
     44
     45#if defined(RTEMS_POSIX_API)
     46  thread_count += rtems_resource_maximum_per_allocation(
     47    Configuration_POSIX_API.maximum_threads
     48  );
     49#endif
     50
     51  return thread_count;
     52}
    3253
    3354void _Workspace_Handler_initialization(
     
    4364  uintptr_t page_size = CPU_HEAP_ALIGNMENT;
    4465  uintptr_t overhead = _Heap_Area_overhead( page_size );
     66  uintptr_t tls_size = (uintptr_t) _TLS_Size;
    4567  size_t i;
     68
     69  if ( tls_size > 0 ) {
     70    uintptr_t tls_alignment = (uintptr_t) _TLS_Alignment;
     71    uintptr_t tls_alloc = _TLS_Get_allocation_size( tls_size, tls_alignment );
     72
     73    remaining += _Get_maximum_thread_count()
     74      * _Heap_Size_with_overhead( page_size, tls_alloc, tls_alignment );
     75  }
    4676
    4777  for (i = 0; i < area_count; ++i) {
  • doc/cpu_supplement/Makefile.am

    r960fd85 r022851a  
    1111REPLACE2 = $(PERL) $(top_srcdir)/tools/word-replace2
    1212
    13 GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \
    14     m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi v850.texi
     13GENERATED_FILES =
     14GENERATED_FILES += general.texi
     15GENERATED_FILES += arm.texi
     16GENERATED_FILES += avr.texi
     17GENERATED_FILES += bfin.texi
     18GENERATED_FILES += h8300.texi
     19GENERATED_FILES += i386.texi
     20GENERATED_FILES += lm32.texi
     21GENERATED_FILES += m32c.texi
     22GENERATED_FILES += m32r.texi
     23GENERATED_FILES += m68k.texi
     24GENERATED_FILES += microblaze.texi
     25GENERATED_FILES += mips.texi
     26GENERATED_FILES += powerpc.texi
     27GENERATED_FILES += nios2.texi
     28GENERATED_FILES += sh.texi
     29GENERATED_FILES += sparc.texi
     30GENERATED_FILES += sparc64.texi
     31GENERATED_FILES += v850.texi
    1532
    1633COMMON_FILES += $(top_srcdir)/common/cpright.texi
     
    4562            -n "" < $< > $@
    4663
     64h8300.texi: h8300.t
     65        $(BMENU2) -p "" \
     66            -u "Top" \
     67            -n "" < $< > $@
     68
    4769i386.texi: i386.t
     70        $(BMENU2) -p "" \
     71            -u "Top" \
     72            -n "" < $< > $@
     73
     74m32c.texi: m32c.t
     75        $(BMENU2) -p "" \
     76            -u "Top" \
     77            -n "" < $< > $@
     78
     79m32r.texi: m32r.t
    4880        $(BMENU2) -p "" \
    4981            -u "Top" \
     
    6092            -n "" < $< > $@
    6193
     94microblaze.texi: microblaze.t
     95        $(BMENU2) -p "" \
     96            -u "Top" \
     97            -n "" < $< > $@
     98
    6299mips.texi: mips.t
    63100        $(BMENU2) -p "" \
     
    66103
    67104powerpc.texi: powerpc.t
     105        $(BMENU2) -p "" \
     106            -u "Top" \
     107            -n "" < $< > $@
     108
     109nios2.texi: nios2.t
    68110        $(BMENU2) -p "" \
    69111            -u "Top" \
  • doc/cpu_supplement/arm.t

    r960fd85 r022851a  
    9898@item executes an infinite loop to simulate a halt processor instruction.
    9999@end itemize
     100
     101@section Thread-Local Storage
     102
     103Thread-local storage is supported.
  • doc/cpu_supplement/avr.t

    r960fd85 r022851a  
    118118@end itemize
    119119
     120@section Thread-Local Storage
     121
     122Thread-local storage is not supported due to a broken tool chain.
     123
    120124@section Board Support Packages
    121125
  • doc/cpu_supplement/bfin.t

    r960fd85 r022851a  
    131131@end itemize
    132132
     133@section Thread-Local Storage
     134
     135Thread-local storage is not implemented.
     136
    133137@section Board Support Packages
    134138
  • doc/cpu_supplement/cpu_supplement.texi

    r960fd85 r022851a  
    6666* Atmel AVR Specific Information::
    6767* Blackfin Specific Information::
     68* Renesas H8/300 Specific Information::
    6869* Intel/AMD x86 Specific Information::
    6970* Lattice Mico32 Specific Information::
     71* Renesas M32C Specific Information::
     72* Renesas M32R Specific Information::
    7073* M68xxx and Coldfire Specific Information::
     74* Xilinx MicroBlaze Specific Information::
    7175* MIPS Specific Information::
     76* Altera Nios II Specific Information::
    7277* PowerPC Specific Information::
    7378* SuperH Specific Information::
     
    8489@include avr.texi
    8590@include bfin.texi
     91@include h8300.texi
    8692@include i386.texi
    8793@include lm32.texi
     94@include m32c.texi
     95@include m32r.texi
    8896@include m68k.texi
     97@include microblaze.texi
    8998@include mips.texi
     99@include nios2.texi
    90100@include powerpc.texi
    91101@include sh.texi
  • doc/cpu_supplement/general.t

    r960fd85 r022851a  
    315315operations of the default CPU specific fatal error handler.
    316316
     317@section Thread-Local Storage
     318
     319In order to support thread-local storage (TLS) the CPU port must implement the
     320facilities mandated by the application binary interface (ABI) of the CPU
     321architecture.  The CPU port must initialize the TLS area in the
     322@code{_CPU_Context_Initialize} function.
     323
     324The board support package (BSP) must provide the following sections and symbols
     325in its linker command file:
     326
     327@example
     328.tdata : @{
     329  _TLS_Data_begin = .;
     330  *(.tdata .tdata.* .gnu.linkonce.td.*)
     331  _TLS_Data_end = .;
     332@}
     333.tbss : @{
     334  _TLS_BSS_begin = .;
     335  *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
     336  _TLS_BSS_end = .;
     337@}
     338_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
     339_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
     340_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
     341_TLS_Alignment = ALIGNOF (.tdata);
     342@end example
     343
    317344@c
    318345@c
  • doc/cpu_supplement/i386.t

    r960fd85 r022851a  
    267267to halt the processor.
    268268
     269@section Thread-Local Storage
     270
     271Thread-local storage is not implemented.
     272
    269273@c
    270274@c
  • doc/cpu_supplement/lm32.t

    r960fd85 r022851a  
    164164operations of the default CPU specific fatal error handler.
    165165
     166@section Thread-Local Storage
     167
     168Thread-local storage is not implemented.
     169
    166170@c
    167171@c
  • doc/cpu_supplement/m68k.t

    r960fd85 r022851a  
    358358@code{stop} instruction to simulate a halt processor instruction.
    359359
     360@section Thread-Local Storage
     361
     362Thread-local storage is supported.
     363
    360364@c
    361365@c
  • doc/cpu_supplement/mips.t

    r960fd85 r022851a  
    123123@code{XXX} instruction to simulate a halt processor instruction.
    124124
     125@section Thread-Local Storage
     126
     127Thread-local storage is not implemented.
     128
    125129@c
    126130@c
  • doc/cpu_supplement/powerpc.t

    r960fd85 r022851a  
    624624@end itemize
    625625
     626@section Thread-Local Storage
     627
     628Thread-local storage is supported.
     629
    626630@c
    627631@c
  • doc/cpu_supplement/sh.t

    r960fd85 r022851a  
    140140instruction to simulate a halt processor instruction.
    141141
     142@section Thread-Local Storage
     143
     144Thread-local storage is not implemented.
     145
    142146@c
    143147@c
  • doc/cpu_supplement/sparc.t

    r960fd85 r022851a  
    918918loop to simulate a halt processor instruction.
    919919
     920@section Thread-Local Storage
     921
     922Thread-local storage is supported.
    920923
    921924@c
  • doc/cpu_supplement/sparc64.t

    r960fd85 r022851a  
    774774loop to simulate a halt processor instruction.
    775775
     776@section Thread-Local Storage
     777
     778Thread-local storage is supported.
    776779
    777780@c
  • doc/cpu_supplement/v850.t

    r960fd85 r022851a  
    103103@item executes a halt processor instruction.
    104104@end itemize
     105
     106@section Thread-Local Storage
     107
     108Thread-local storage is not implemented.
  • testsuites/sptests/Makefile.am

    r960fd85 r022851a  
    3131    spcbssched01 spcbssched02 spcbssched03 spqreslib sptimespec01 \
    3232    spregion_err01 sppartition_err01
     33if HAS_CPLUSPLUS
     34SUBDIRS += sptls02
     35endif
     36SUBDIRS += sptls01
    3337SUBDIRS += spintrcritical20
    3438SUBDIRS += spintrcritical19
  • testsuites/sptests/configure.ac

    r960fd85 r022851a  
    1212AM_MAINTAINER_MODE
    1313
     14RTEMS_ENABLE_CXX
    1415RTEMS_ENV_RTEMSBSP
    1516RTEMS_CHECK_RTEMS_TEST_NO_PAUSE
     
    1819
    1920RTEMS_PROG_CC_FOR_TARGET
     21RTEMS_PROG_CXX_FOR_TARGET
    2022
    2123RTEMS_CANONICALIZE_TOOLS
    2224
    2325RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
     26RTEMS_CHECK_CXX(RTEMS_BSP)
     27
     28AM_CONDITIONAL([HAS_CPLUSPLUS],[test $HAS_CPLUSPLUS = "yes"])
    2429
    2530# FIXME: We should get rid of this. It's a cludge.
     
    3237# Explicitly list all Makefiles here
    3338AC_CONFIG_FILES([Makefile
     39sptls02/Makefile
     40sptls01/Makefile
    3441spintrcritical20/Makefile
    3542spintrcritical19/Makefile
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