Changeset 42e243e in rtems


Ignore:
Timestamp:
Dec 4, 2009, 4:27:21 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
5bb38e15
Parents:
06731d6
Message:

Whitespace removal.

Files:
59 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/i386/cpu.h

    r06731d6 r42e243e  
    11/*
    2  * cpu.h  - This file contains definitions for data structure related 
     2 * cpu.h  - This file contains definitions for data structure related
    33 *          to Intel system programming. More information can be found
    44 *          on Intel site and more precisely in the following book :
     
    148148
    149149/*
    150  * Type definition for raw interrupts. 
     150 * Type definition for raw interrupts.
    151151 */
    152152
     
    168168   * board specific hardware to manage interrupts and thus the
    169169   * "on" routine must enable the irq both at device and PIC level.
    170    * 
    171    */
    172     rtems_raw_irq_enable        on;     
     170   *
     171   */
     172    rtems_raw_irq_enable        on;
    173173  /*
    174174   * function for disabling raw interrupts. In order to be consistent
     
    177177   * board specific hardware to manage interrupts and thus the
    178178   * "on" routine must disable the irq both at device and PIC level.
    179    * 
     179   *
    180180   */
    181181  rtems_raw_irq_disable         off;
     
    205205/*
    206206 * C callable function enabling to get handler currently connected to a vector
    207  * 
     207 *
    208208 */
    209209rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset);
     
    336336  unsigned int          table_entry;
    337337} page_table_entry;
    338  
     338
    339339/*
    340340 * definitions related to page table entry
     
    372372extern int      _CPU_map_phys_address
    373373                      (void **mappedAddress, void *physAddress,
    374                        int size, int flag); 
    375 extern int      _CPU_unmap_virt_address (void *mappedAddress, int size); 
     374                       int size, int flag);
     375extern int      _CPU_unmap_virt_address (void *mappedAddress, int size);
    376376extern int      _CPU_change_memory_mapping_attribute
    377377                         (void **newAddress, void *mappedAddress,
    378378                          unsigned int size, unsigned int flag);
    379 extern int      _CPU_display_memory_attribute(); 
     379extern int      _CPU_display_memory_attribute();
    380380
    381381# endif /* ASM */
  • c/src/lib/libcpu/i386/cpuModel.S

    r06731d6 r42e243e  
    66 *  Intel also provides public similar code in the book
    77 *  called :
    8  *     
     8 *
    99 *      Pentium Processor Family
    1010 *              Developer Family
     
    1212 *
    1313 * At the following place :
    14  *     
     14 *
    1515 *      Chapter 5 :     Feature determination
    16  *      Chapter 25:     CPUID instruction       
     16 *      Chapter 25:     CPUID instruction
    1717 *
    1818 *  COPYRIGHT (c) 1998 valette@crf.canon.fr
     
    2929
    3030BEGIN_CODE
    31         PUBLIC(checkCPUtypeSetCr0); 
    32 /* 
    33  * check Processor type: 386, 486, 6x86(L) or CPUID capable processor 
     31        PUBLIC(checkCPUtypeSetCr0);
     32/*
     33 * check Processor type: 386, 486, 6x86(L) or CPUID capable processor
    3434 */
    3535
    3636SYM (checkCPUtypeSetCr0):
    3737        /*
    38          *  Assume 386 for now 
    39          */
    40         movl $3, SYM (x86) 
     38         *  Assume 386 for now
     39         */
     40        movl $3, SYM (x86)
    4141        /*
    4242         * Start using the EFLAGS AC bit determination method described in
     
    4545         */
    4646        pushfl                          /* save EFLAGS                  */
    47        
     47
    4848        pushfl                          /* Get EFLAGS in EAX            */
    4949        popl eax
    50        
     50
    5151        movl eax,ecx                    /* save original EFLAGS in ECX  */
    5252        xorl $EFLAGS_ALIGN_CHECK,eax    /* flip AC bit in EAX           */
    5353        pushl eax                       /* set EAX as EFLAGS            */
    54         popfl                   
     54        popfl
    5555        pushfl                          /* Get new EFLAGS in EAX        */
    5656        popl eax
    57        
     57
    5858        xorl ecx,eax                    /* check if AC bit changed      */
    59         andl $EFLAGS_ALIGN_CHECK,eax   
     59        andl $EFLAGS_ALIGN_CHECK,eax
    6060        je is386                        /* If not : we have a 386       */
    6161        /*
    62          *  Assume 486 for now 
     62         *  Assume 486 for now
    6363         */
    6464        movl $4,SYM (x86)
     
    6666        xorl $EFLAGS_ID,eax             /* flip  ID flag                */
    6767        pushl eax                       /* set EAX as EFLAGS            */
    68         popfl                           
     68        popfl
    6969        pushfl                          /* Get new EFLAGS in EAX        */
    70         popl eax       
    71                        
     70        popl eax
     71
    7272        xorl ecx,eax                    /* check if ID bit changed      */
    7373        andl $EFLAGS_ID,eax
    7474
    75         /* 
     75        /*
    7676         * if we are on a straight 486DX,
    7777         * SX, or 487SX we can't change it
    78          * OTOH 6x86MXs and MIIs check OK 
     78         * OTOH 6x86MXs and MIIs check OK
    7979         * Also if we are on a Cyrix 6x86(L)
    8080         */
    8181        je is486x
    8282
    83 isnew: 
     83isnew:
    8484        /*
    8585         * restore original EFLAGS
     
    8888        incl SYM(have_cpuid)    /* we have CPUID instruction */
    8989
    90         /* use it to get :     
     90        /* use it to get :
    9191         *      processor type,
    9292         *      processor model,
     
    9494         * by using it with EAX = 1
    9595         */
    96         movl $1, eax           
    97         cpuid                   
     96        movl $1, eax
     97        cpuid
    9898        movl ecx,SYM(x86_capability_x) /* store ecx feature flags */
    9999
    100100        movb al, cl             /* save reg for future use */
    101        
     101
    102102        andb $0x0f,ah           /* mask processor family   */
    103103        movb ah,SYM (x86)       /* put result in x86 var   */
    104        
     104
    105105        andb $0xf0, al          /* get model               */
    106106        shrb $4, al
    107107        movb al,SYM (x86_model) /* store it in x86_model   */
    108        
     108
    109109        andb $0x0f, cl          /* get mask revision       */
    110110        movb cl,SYM (x86_mask)  /* store it in x86_mask    */
    111        
     111
    112112        movl edx,SYM(x86_capability)    /* store feature flags in x86_capability */
    113        
     113
    114114        /* get vendor info by using CPUID with EXA = 0 */
    115         xorl eax, eax           
     115        xorl eax, eax
    116116        cpuid
    117117
     
    120120         * x86_vendor_id variable.
    121121         */
    122         movl ebx,SYM(x86_vendor_id)     
    123         movl edx,SYM(x86_vendor_id)+4   
    124         movl ecx,SYM(x86_vendor_id)+8   
     122        movl ebx,SYM(x86_vendor_id)
     123        movl edx,SYM(x86_vendor_id)+4
     124        movl ecx,SYM(x86_vendor_id)+8
    125125
    126126        movl cr0,eax            /* 486+ */
     
    181181        getCx86($0xfe)          /* DIR0 : let's check this is a 6x86(L) */
    182182        andb $0xf0,al           /* should be 3xh */
    183         cmpb $0x30,al           
     183        cmpb $0x30,al
    184184        jne n6x86
    185185        getCx86($0xe9)          /* CCR5 : we reset the SLOP bit */
     
    207207        call check_x87
    208208        ret
    209        
     209
    210210
    211211/*
     
    229229
    230230END_CODE
    231        
     231
    232232BEGIN_DATA
    233233        PUBLIC(x86)
     
    240240        PUBLIC(hard_math)
    241241
    242 SYM(x86):       
    243         .byte 0
    244 SYM(have_cpuid):       
     242SYM(x86):
     243        .byte 0
     244SYM(have_cpuid):
    245245        .long 0
    246 SYM(x86_model): 
    247         .byte 0
    248 SYM(x86_mask): 
    249         .byte 0
    250 SYM(x86_capability):   
    251         .long 0         
    252 SYM(x86_capability_x): 
    253         .long 0         
    254 SYM(x86_vendor_id):     
     246SYM(x86_model):
     247        .byte 0
     248SYM(x86_mask):
     249        .byte 0
     250SYM(x86_capability):
     251        .long 0
     252SYM(x86_capability_x):
     253        .long 0
     254SYM(x86_vendor_id):
    255255        .zero 13
    256 SYM(hard_math): 
     256SYM(hard_math):
    257257        .byte 0
    258258END_DATA
  • c/src/lib/libcpu/i386/cpuModel.h

    r06731d6 r42e243e  
    2828extern int x86_capability_x;    /* cpuid:ECX */
    2929extern char x86_vendor_id[13];
    30 extern int have_cpuid; 
     30extern int have_cpuid;
    3131extern unsigned char Cx86_step; /* cyrix processor identification */
    3232
  • c/src/lib/libcpu/i386/displayCpu.c

    r06731d6 r42e243e  
    135135        const char *p=NULL;
    136136        int i;
    137        
     137
    138138        if (x86_model < 16)
    139139                for (i=0; i<sizeof(amd_models)/sizeof(struct cpu_model_info); i++)
     
    188188        "24",  "25", "26", "27", "28", "29", "30", "31"
    189189  };
    190          
    191   printk("cpu         : %c86\n", x86+'0'); 
     190
     191  printk("cpu         : %c86\n", x86+'0');
    192192  printk("model       : %s\n",
    193193         have_cpuid ? getmodel(x86, x86_model) : "unknown");
     
    195195    strcpy(x86_vendor_id, "unknown");
    196196  printk("vendor_id   : %s\n", x86_vendor_id);
    197        
     197
    198198  if (x86_mask)
    199199    if (strncmp(x86_vendor_id, "Cyrix", 5) != 0) {
     
    205205  else
    206206    printk("stepping    : unknown\n");
    207        
     207
    208208  printk("fpu         : %s\n", (hard_math ? "yes" : "no"));
    209209  printk("cpuid       : %s\n", (have_cpuid ? "yes" : "no"));
  • c/src/lib/libcpu/i386/idtr.S

    r06731d6 r42e243e  
    2727PUBLIC (i386_get_info_from_GDTR)
    2828PUBLIC (i386_set_GDTR)
    29                
     29
    3030SYM (i386_get_info_from_IDTR):
    3131        movl    4(esp), ecx         /* get location where table address */
     
    5353                           unsigned limit);
    5454 */
    55 SYM (i386_set_IDTR):                   
     55SYM (i386_set_IDTR):
    5656
    5757        leal    4(esp), edx         /* load in edx address of input */
     
    7474                                     unsigned* limit);
    7575 */
    76        
    77 SYM (i386_get_info_from_GDTR): 
     76
     77SYM (i386_get_info_from_GDTR):
    7878        movl    4(esp), ecx         /* get location where table address */
    7979                                    /*    must be stored */
     
    9898 *   extern void i386_set_GDTR (segment_descriptors*, unsigned limit);
    9999 */
    100 SYM (i386_set_GDTR):                   
     100SYM (i386_set_GDTR):
    101101
    102102        leal    4(esp), edx         /* load in edx address of input */
     
    112112
    113113        ret
    114                
     114
    115115END_CODE
    116116
  • c/src/lib/libcpu/i386/page.c

    r06731d6 r42e243e  
    8181  unsigned int physPage;
    8282  int nbTables=0;
    83  
     83
    8484  /*
    8585   * rtemsFreeMemStart is the last valid 32-bits address
     
    8787   */
    8888  memorySize = rtemsFreeMemStart + 4;
    89  
     89
    9090  nbPages = ( (memorySize - 1) / PG_SIZE ) + 1;
    9191  nbTables = ( (memorySize - 1) / FOUR_MB ) + 2;
    9292
    9393  /* allocate 1 page more to page alignement */
    94   Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) ); 
     94  Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) );
    9595  if ( Tables == NULL ){
    9696    return -1; /*unable to allocate memory */
    9797  }
    98  
     98
    9999  /* 4K-page alignement */
    100100  Tables += (PG_SIZE - (int)Tables) & 0xFFF;
     
    140140      pageTable ++;
    141141    }
    142      
     142
    143143    nbInitPages++;
    144144  }
     
    150150  i386_set_cr3( regCr3.i );
    151151
    152   _CPU_enable_cache(); 
    153   _CPU_enable_paging(); 
     152  _CPU_enable_cache();
     153  _CPU_enable_paging();
    154154
    155155  return 0;
     
    190190  int    flag
    191191)
    192 { 
     192{
    193193  page_table *localPageTable;
    194194  unsigned int lastAddress, countAddress;
     
    196196  linear_address virtualAddress;
    197197  unsigned char pagingWasEnabled;
    198  
     198
    199199  pagingWasEnabled = 0;
    200200
     
    216216    if (pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address == 0){
    217217      /* We allocate 2 pages to perform 4k-page alignement */
    218       Tables = (char *)malloc(2*sizeof(page_table)); 
     218      Tables = (char *)malloc(2*sizeof(page_table));
    219219      if ( Tables == NULL ){
    220220        if (pagingWasEnabled)
     
    226226
    227227      /* Reset Table */
    228       memset( Tables, 0, sizeof(page_table) );     
     228      memset( Tables, 0, sizeof(page_table) );
    229229      pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address =
    230230        (unsigned int)Tables >> 12;
     
    238238      pageDirectory->pageDirEntry[directoryEntry].bits.present        = 1;
    239239    }
    240      
     240
    241241
    242242    localPageTable = (page_table *)(pageDirectory->
     
    265265    countAddress += PG_SIZE;
    266266    tableEntry++;
    267     if (tableEntry >= MAX_ENTRY){     
     267    if (tableEntry >= MAX_ENTRY){
    268268      tableEntry = 0;
    269269      directoryEntry++;
     
    286286  unsigned int dirCount, pageCount;
    287287  page_table *localPageTable;
    288  
     288
    289289  if (tableEntry == 0){
    290290    dirCount  = directoryEntry - 1;
     
    295295    pageCount = tableEntry - 1;
    296296  }
    297    
     297
    298298  while (1){
    299299
     
    304304    if (localPageTable->pageTableEntry[pageCount].bits.present == 1){
    305305      pageCount++;
    306       if (pageCount >= MAX_ENTRY){     
     306      if (pageCount >= MAX_ENTRY){
    307307        pageCount = 0;
    308308        dirCount++;
     
    313313
    314314    if (pageCount == 0) {
    315       if (dirCount == 0){       
     315      if (dirCount == 0){
    316316        break;
    317317      }
     
    319319        pageCount = MAX_ENTRY - 1;
    320320        dirCount-- ;
    321       } 
     321      }
    322322    }
    323323    else
     
    328328  tableEntry = pageCount;
    329329}
    330      
    331  
     330
     331
    332332/*
    333333 * Unmap the virtual address from the tables
     
    339339  int   size
    340340)
    341 { 
     341{
    342342
    343343  linear_address linearAddr;
     
    346346  unsigned int dirCount ;
    347347  unsigned char pagingWasEnabled;
    348  
     348
    349349  pagingWasEnabled = 0;
    350350
     
    372372                                    pageDirEntry[linearAddr.bits.directory].bits.
    373373                                    page_frame_address << 12);
    374    
     374
    375375    if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){
    376376      if (pagingWasEnabled)
     
    378378      return -1;
    379379    }
    380  
    381     localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0;   
    382    
     380
     381    localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0;
     382
    383383    linearAddr.address += PG_SIZE ;
    384384  }
     
    391391
    392392/*
    393  * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE 
     393 * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE
    394394 * of the page's descriptor.
    395395 */
     
    401401  unsigned int   flag
    402402)
    403 { 
     403{
    404404
    405405  linear_address linearAddr;
     
    407407  unsigned int lastAddr ;
    408408  unsigned char pagingWasEnabled;
    409  
     409
    410410  pagingWasEnabled = 0;
    411411
     
    414414    _CPU_disable_paging();
    415415  }
    416  
     416
    417417  linearAddr.address  = (unsigned int)mappedAddress;
    418418  lastAddr = (unsigned int)mappedAddress + (size - 1);
     
    431431                                    pageDirEntry[linearAddr.bits.directory].bits.
    432432                                    page_frame_address << 12);
    433    
     433
    434434    if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){
    435435      if (pagingWasEnabled)
     
    437437      return -1;
    438438    }
    439  
     439
    440440    localPageTable->pageTableEntry[linearAddr.bits.page].table_entry &= ~MASK_FLAGS ;
    441441    localPageTable->pageTableEntry[linearAddr.bits.page].table_entry |= flag ;
    442    
     442
    443443    linearAddr.address += PG_SIZE ;
    444   } 
     444  }
    445445
    446446  if (newAddress != NULL)
     
    461461
    462462int  _CPU_display_memory_attribute(void)
    463 { 
     463{
    464464  unsigned int dirCount, pageCount;
    465465  cr0 regCr0;
     
    469469  unsigned int maxPage;
    470470  unsigned char pagingWasEnabled;
    471  
     471
    472472  regCr0.i = i386_get_cr0();
    473  
     473
    474474  printk("\n\n********* MEMORY CACHE CONFIGURATION *****\n");
    475475
     
    479479  if (regCr0.cr0.paging == 0)
    480480    return 0;
    481  
     481
    482482  prevPresent = 0;
    483483  prevCache   = 1;
    484  
     484
    485485  pagingWasEnabled = 0;
    486486
  • c/src/lib/libcpu/m68k/m68040/fpsp/bindec.S

    r06731d6 r42e243e  
    2222//      Algorithm:
    2323//
    24 //      A1.     Set RM and size ext;  Set SIGMA = sign of input. 
     24//      A1.     Set RM and size ext;  Set SIGMA = sign of input.
    2525//              The k-factor is saved for use in d7. Clear the
    2626//              BINDEC_FLG for separating normalized/denormalized
     
    3232//      A3.     Compute ILOG.
    3333//              ILOG is the log base 10 of the input value.  It is
    34 //              approximated by adding e + 0.f when the original 
    35 //              value is viewed as 2^^e * 1.f in extended precision. 
     34//              approximated by adding e + 0.f when the original
     35//              value is viewed as 2^^e * 1.f in extended precision.
    3636//              This value is stored in d6.
    3737//
    3838//      A4.     Clr INEX bit.
    39 //              The operation in A3 above may have set INEX2. 
     39//              The operation in A3 above may have set INEX2.
    4040//
    4141//      A5.     Set ICTR = 0;
    42 //              ICTR is a flag used in A13.  It must be set before the 
     42//              ICTR is a flag used in A13.  It must be set before the
    4343//              loop entry A6.
    4444//
     
    6262//
    6363//      A8.     Clr INEX; Force RZ.
    64 //              The operation in A3 above may have set INEX2. 
     64//              The operation in A3 above may have set INEX2.
    6565//              RZ mode is forced for the scaling operation to insure
    66 //              only one rounding error.  The grs bits are collected in 
     66//              only one rounding error.  The grs bits are collected in
    6767//              the INEX flag for use in A10.
    6868//
     
    9393//
    9494//      A14.    Convert the mantissa to bcd.
    95 //              The binstr routine is used to convert the LEN digit 
     95//              The binstr routine is used to convert the LEN digit
    9696//              mantissa to bcd in memory.  The input to binstr is
    9797//              to be a fraction; i.e. (mantissa)/10^LEN and adjusted
    9898//              such that the decimal point is to the left of bit 63.
    99 //              The bcd digits are stored in the correct position in 
     99//              The bcd digits are stored in the correct position in
    100100//              the final string area in memory.
    101101//
     
    134134//                      All Rights Reserved
    135135//
    136 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    137 //      The copyright notice above does not evidence any 
     136//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     137//      The copyright notice above does not evidence any
    138138//      actual or intended publication of such source code.
    139139
     
    174174//     is a denormalized number, set the BINDEC_FLG memory word
    175175//     to signal denorm.  If the input is unnormalized, normalize
    176 //     the input and test for denormalized result. 
     176//     the input and test for denormalized result.
    177177//
    178178        fmovel  #rm_mode,%FPCR  //set RM and ext
     
    254254        faddw   %d0,%fp0                //add in exp
    255255        fsubs   FONE,%fp0       //subtract off 1.0
    256         fbge    pos_res         //if pos, branch 
     256        fbge    pos_res         //if pos, branch
    257257        fmulx   LOG2UP1,%fp0    //if neg, mul by LOG2UP1
    258258        fmovel  %fp0,%d6                //put ILOG in d6 as a lword
     
    264264
    265265// A4. Clr INEX bit.
    266 //     The operation in A3 above may have set INEX2. 
    267 
    268 A4_str: 
     266//     The operation in A3 above may have set INEX2.
     267
     268A4_str:
    269269        fmovel  #0,%FPSR                //zero all of fpsr - nothing needed
    270270
    271271
    272272// A5. Set ICTR = 0;
    273 //     ICTR is a flag used in A13.  It must be set before the 
     273//     ICTR is a flag used in A13.  It must be set before the
    274274//     loop entry A6. The lower word of d5 is used for ICTR.
    275275
     
    306306//      L_SCR2:first word of X packed/Unchanged
    307307
    308 A6_str: 
     308A6_str:
    309309        tstl    %d7             //branch on sign of k
    310310        bles    k_neg           //if k <= 0, LEN = ILOG + 1 - k
     
    378378//      L_SCR2:first word of X packed/Unchanged
    379379
    380 A7_str: 
     380A7_str:
    381381        tstl    %d7             //test sign of k
    382382        bgts    k_pos           //if pos and > 0, skip this
     
    384384        blts    k_pos           //if ILOG >= k, skip this
    385385        movel   %d7,%d6         //if ((k<0) & (ILOG < k)) ILOG = k
    386 k_pos: 
     386k_pos:
    387387        movel   %d6,%d0         //calc ILOG + 1 - LEN in d0
    388388        addql   #1,%d0          //add the 1
     
    398398        addil   #24,%d0         //add in 24 to iscale
    399399        movel   #24,%d2         //put 24 in d2 for A9
    400 no_inf: 
     400no_inf:
    401401        negl    %d0             //and take abs of ISCALE
    402 iscale: 
     402iscale:
    403403        fmoves  FONE,%fp1       //init fp1 to 1
    404404        bfextu  USER_FPCR(%a6){#26:#2},%d1 //get initial rmode bits
     
    428428rmode:
    429429        clrl    %d3             //clr table index
    430 e_loop: 
     430e_loop:
    431431        lsrl    #1,%d0          //shift next bit into carry
    432432        bccs    e_next          //if zero, skip the mul
    433433        fmulx   (%a1,%d3),%fp1  //mul by 10**(d3_bit_no)
    434 e_next: 
     434e_next:
    435435        addl    #12,%d3         //inc d3 to next pwrten table entry
    436436        tstl    %d0             //test if ISCALE is zero
     
    439439
    440440// A8. Clr INEX; Force RZ.
    441 //     The operation in A3 above may have set INEX2. 
     441//     The operation in A3 above may have set INEX2.
    442442//     RZ mode is forced for the scaling operation to insure
    443 //     only one rounding error.  The grs bits are collected in 
     443//     only one rounding error.  The grs bits are collected in
    444444//     the INEX flag for use in A10.
    445445//
     
    447447//      Input/Output
    448448
    449         fmovel  #0,%FPSR                //clr INEX 
     449        fmovel  #0,%FPSR                //clr INEX
    450450        fmovel  #rz_mode,%FPCR  //set RZ rounding mode
    451451
     
    454454//     The mantissa is scaled to the desired number of significant
    455455//     digits.  The excess digits are collected in INEX2. If mul,
    456 //     Check d2 for excess 10 exponential value.  If not zero, 
     456//     Check d2 for excess 10 exponential value.  If not zero,
    457457//     the iscale value would have caused the pwrten calculation
    458458//     to overflow.  Only a negative iscale can cause this, so
     
    483483//      L_SCR2:first word of X packed/Unchanged
    484484
    485 A9_str: 
     485A9_str:
    486486        fmovex  (%a0),%fp0      //load X from memory
    487487        fabsx   %fp0            //use abs(X)
     
    501501A9_loop:
    502502        clrl    -(%a7)          //clear lword on stack
    503         dbf     %d3,A9_loop     
     503        dbf     %d3,A9_loop
    504504        moveb   VER_TMP(%a6),(%a7) //write current version number
    505         moveb   #BUSY_SIZE-4,1(%a7) //write current busy size 
     505        moveb   #BUSY_SIZE-4,1(%a7) //write current busy size
    506506        moveb   #0x10,0x44(%a7) //set fcefpte[15] bit
    507507        movew   #0x0023,0x40(%a7)       //load cmdreg1b with mul command
     
    540540//      fp2: x/x
    541541
    542 A10_st: 
     542A10_st:
    543543        fmovel  %FPSR,%d0               //get FPSR
    544544        fmovex  %fp0,FP_SCR2(%a6)       //move Y to memory
     
    556556//      mode and precision.  The original FPCR is saved in L_SCR1.
    557557
    558 A11_st: 
     558A11_st:
    559559        movel   USER_FPCR(%a6),L_SCR1(%a6) //save it for later
    560         andil   #0x00000030,USER_FPCR(%a6) //set size to ext, 
     560        andil   #0x00000030,USER_FPCR(%a6) //set size to ext,
    561561//                                      ;block exceptions
    562562
     
    587587
    588588A12_st:
    589         moveml  %d0-%d1/%a0-%a1,-(%a7)  //save regs used by sintd0     
     589        moveml  %d0-%d1/%a0-%a1,-(%a7)  //save regs used by sintd0
    590590        movel   L_SCR1(%a6),-(%a7)
    591591        movel   L_SCR2(%a6),-(%a7)
     
    593593        fmovex  %fp0,(%a0)              //move Y to memory at FP_SCR2(a6)
    594594        tstl    L_SCR2(%a6)             //test sign of original operand
    595         bges    do_fint                 //if pos, use Y 
     595        bges    do_fint                 //if pos, use Y
    596596        orl     #0x80000000,(%a0)               //if neg, use -Y
    597597do_fint:
     
    602602        movel   (%a7)+,L_SCR2(%a6)
    603603        movel   (%a7)+,L_SCR1(%a6)
    604         moveml  (%a7)+,%d0-%d1/%a0-%a1  //restore regs used by sint     
     604        moveml  (%a7)+,%d0-%d1/%a0-%a1  //restore regs used by sint
    605605        movel   L_SCR2(%a6),FP_SCR2(%a6)        //restore original exponent
    606606        movel   L_SCR1(%a6),USER_FPCR(%a6) //restore user's FPCR
     
    638638//      L_SCR2:first word of X packed/Unchanged
    639639
    640 A13_st: 
     640A13_st:
    641641        swap    %d5             //put ICTR in lower word of d5
    642642        tstw    %d5             //check if ICTR = 0
     
    649649        subql   #1,%d0          //d0 = LEN -1
    650650        clrl    %d3             //clr table index
    651 l_loop: 
     651l_loop:
    652652        lsrl    #1,%d0          //shift next bit into carry
    653653        bccs    l_next          //if zero, skip the mul
     
    675675        movew   #1,%d5          //set ICTR
    676676        fmovel  #rm_mode,%FPCR  //set rmode to RM
    677         fmuls   FTEN,%fp2       //compute 10^LEN 
     677        fmuls   FTEN,%fp2       //compute 10^LEN
    678678        bra     A6_str          //return to A6 and recompute YINT
    679679test_2:
     
    691691        bra     A6_str          //return to A6 and recompute YINT
    692692//
    693 // Since ICTR <> 0, we have already been through one adjustment, 
     693// Since ICTR <> 0, we have already been through one adjustment,
    694694// and shouldn't have another; this is to check if abs(YINT) = 10^LEN
    695695// 10^LEN is again computed using whatever table is in a1 since the
     
    718718
    719719// A14. Convert the mantissa to bcd.
    720 //      The binstr routine is used to convert the LEN digit 
     720//      The binstr routine is used to convert the LEN digit
    721721//      mantissa to bcd in memory.  The input to binstr is
    722722//      to be a fraction; i.e. (mantissa)/10^LEN and adjusted
    723723//      such that the decimal point is to the left of bit 63.
    724 //      The bcd digits are stored in the correct position in 
     724//      The bcd digits are stored in the correct position in
    725725//      the final string area in memory.
    726726//
     
    748748//      L_SCR2:first word of X packed/Unchanged
    749749
    750 A14_st: 
     750A14_st:
    751751        fmovel  #rz_mode,%FPCR  //force rz for conversion
    752752        fdivx   %fp2,%fp0               //divide abs(YINT) by 10^LEN
     
    765765        negl    %d0             //make exp positive
    766766m_loop:
    767         lsrl    #1,%d2          //shift d2:d3 right, add 0s 
     767        lsrl    #1,%d2          //shift d2:d3 right, add 0s
    768768        roxrl   #1,%d3          //the number of places
    769769        dbf     %d0,m_loop      //given in d0
     
    820820//      L_SCR2:first word of X packed/Unchanged
    821821
    822 A15_st: 
     822A15_st:
    823823        tstb    BINDEC_FLG(%a6) //check for denorm
    824824        beqs    not_denorm
     
    842842        fmoves  FONE,%fp0       //force exponent to 1
    843843        bras    convrt          //do it
    844 not_zero:       
     844not_zero:
    845845        fmovel  %d6,%fp0                //float ILOG
    846846        fabsx   %fp0            //get abs of ILOG
     
    855855        negw    %d0             //make exp positive
    856856x_loop:
    857         lsrl    #1,%d2          //shift d2:d3 right 
     857        lsrl    #1,%d2          //shift d2:d3 right
    858858        roxrl   #1,%d3          //the number of places
    859859        dbf     %d0,x_loop      //given in d0
     
    866866        leal    L_SCR1(%a6),%a0 //a0 is ptr to L_SCR1 for exp digits
    867867        bsr     binstr          //call binstr to convert exp
    868         movel   L_SCR1(%a6),%d0 //load L_SCR1 lword to d0 
     868        movel   L_SCR1(%a6),%d0 //load L_SCR1 lword to d0
    869869        movel   #12,%d1         //use d1 for shift count
    870870        lsrl    %d1,%d0         //shift d0 right by 12
    871871        bfins   %d0,FP_SCR1(%a6){#4:#12} //put e3:e2:e1 in FP_SCR1
    872872        lsrl    %d1,%d0         //shift d0 right by 12
    873         bfins   %d0,FP_SCR1(%a6){#16:#4} //put e4 in FP_SCR1 
     873        bfins   %d0,FP_SCR1(%a6){#16:#4} //put e4 in FP_SCR1
    874874        tstb    %d0             //check if e4 is zero
    875875        beqs    A16_st          //if zero, skip rest
     
    902902A16_st:
    903903        clrl    %d0             //clr d0 for collection of signs
    904         andib   #0x0f,FP_SCR1(%a6) //clear first nibble of FP_SCR1 
     904        andib   #0x0f,FP_SCR1(%a6) //clear first nibble of FP_SCR1
    905905        tstl    L_SCR2(%a6)     //check sign of original mantissa
    906906        bges    mant_p          //if pos, don't set SM
     
    909909        tstl    %d6             //check sign of ILOG
    910910        bges    wr_sgn          //if pos, don't set SE
    911         addql   #1,%d0          //set bit 0 in d0 for SE 
     911        addql   #1,%d0          //set bit 0 in d0 for SE
    912912wr_sgn:
    913913        bfins   %d0,FP_SCR1(%a6){#0:#2} //insert SM and SE into FP_SCR1
  • c/src/lib/libcpu/m68k/m68040/fpsp/binstr.S

    r06731d6 r42e243e  
    6262//                      All Rights Reserved
    6363//
    64 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    65 //      The copyright notice above does not evidence any 
     64//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     65//      The copyright notice above does not evidence any
    6666//      actual or intended publication of such source code.
    6767
  • c/src/lib/libcpu/m68k/m68040/fpsp/bugfix.S

    r06731d6 r42e243e  
    99//      Fixes for bugs: 1238
    1010//
    11 //      Bug: 1238 
     11//      Bug: 1238
    1212//
    1313//
     
    154154//                      All Rights Reserved
    155155//
    156 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    157 //      The copyright notice above does not evidence any 
     156//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     157//      The copyright notice above does not evidence any
    158158//      actual or intended publication of such source code.
    159159
     
    169169b1238_fix:
    170170//
    171 // This code is entered only on completion of the handling of an 
    172 // nu-generated ovfl, unfl, or inex exception.  If the version 
     171// This code is entered only on completion of the handling of an
     172// nu-generated ovfl, unfl, or inex exception.  If the version
    173173// number of the fsave is not $40, this handler is not necessary.
    174174// Simply branch to fix_done and exit normally.
     
    186186//
    187187// Test the register conflict aspect.  If opclass0, check for
    188 // cu src equal to xu dest or equal to nu dest.  If so, go to 
     188// cu src equal to xu dest or equal to nu dest.  If so, go to
    189189// op0.  Else, or if opclass2, check for cu dest equal to
    190190// xu dest or equal to nu dest.  If so, go to tst_opcl.  Else,
     
    198198//
    199199// Check for cu and nu register conflict.  If one exists, this takes
    200 // priority over a cu and xu conflict. 
    201 //
    202         bfextu  CMDREG1B(%a6){#3:#3},%d0        //get 1st src 
     200// priority over a cu and xu conflict.
     201//
     202        bfextu  CMDREG1B(%a6){#3:#3},%d0        //get 1st src
    203203        bfextu  CMDREG3B(%a6){#6:#3},%d1        //get 3rd dest
    204204        cmpb    %d0,%d1
    205205        beqs    op0                     //if equal, continue bugfix
    206206//
    207 // Check for cu dest equal to nu dest.  If so, go and fix the 
     207// Check for cu dest equal to nu dest.  If so, go and fix the
    208208// bug condition.  Otherwise, exit.
    209209//
    210         bfextu  CMDREG1B(%a6){#6:#3},%d0        //get 1st dest 
     210        bfextu  CMDREG1B(%a6){#6:#3},%d0        //get 1st dest
    211211        cmpb    %d0,%d1                 //cmp 1st dest with 3rd dest
    212212        beqs    op0                     //if equal, continue bugfix
     
    217217        cmpb    %d0,%d1                 //cmp 1st dest with 2nd dest
    218218        beqs    op0_xu                  //if equal, continue bugfix
    219         bfextu  CMDREG1B(%a6){#3:#3},%d0        //get 1st src 
     219        bfextu  CMDREG1B(%a6){#3:#3},%d0        //get 1st src
    220220        cmpb    %d0,%d1                 //cmp 1st src with 2nd dest
    221221        beq     op0_xu
     
    247247//
    248248// We have the case in which a conflict exists between the cu src or
    249 // dest and the dest of the xu.  We must clear the instruction in 
     249// dest and the dest of the xu.  We must clear the instruction in
    250250// the cu and restore the state, allowing the instruction in the
    251251// xu to complete.  Remember, the instruction in the nu
     
    257257//
    258258//      Items saved from the stack:
    259 //     
     259//
    260260//              $3c stag     - L_SCR1
    261261//              $40 cmdreg1b - L_SCR2
     
    266266//
    267267op0_xu:
    268         movel   STAG(%a6),L_SCR1(%a6)   
    269         movel   CMDREG1B(%a6),L_SCR2(%a6)       
     268        movel   STAG(%a6),L_SCR1(%a6)
     269        movel   CMDREG1B(%a6),L_SCR2(%a6)
    270270        movel   DTAG(%a6),L_SCR3(%a6)
    271271        andil   #0xe0000000,L_SCR3(%a6)
     
    276276//
    277277// Check if the instruction which just completed was exceptional.
    278 // 
     278//
    279279        cmpw    #0x4060,(%a7)
    280280        beq     op0_xb
    281 // 
     281//
    282282// It is necessary to isolate the result of the instruction in the
    283283// xu if it is to fp0 - fp3 and write that value to the USER_FPn
    284 // locations on the stack.  The correct destination register is in 
     284// locations on the stack.  The correct destination register is in
    285285// cmdreg2b.
    286286//
     
    341341//
    342342// The frame returned is busy.  It is not possible to reconstruct
    343 // the code sequence to allow completion.  We will jump to 
     343// the code sequence to allow completion.  We will jump to
    344344// fpsp_fmt_error and allow the kernel to kill the process.
    345345//
     
    356356        bne     fix_done                //if not, it is not bug 1238
    357357//
    358 // Check for cu dest equal to nu dest or equal to xu dest, with 
     358// Check for cu dest equal to nu dest or equal to xu dest, with
    359359// a cu and nu conflict taking priority an nu conflict.  If either,
    360360// go and fix the bug condition.  Otherwise, exit.
    361361//
    362         bfextu  CMDREG1B(%a6){#6:#3},%d0        //get 1st dest 
     362        bfextu  CMDREG1B(%a6){#6:#3},%d0        //get 1st dest
    363363        bfextu  CMDREG3B(%a6){#6:#3},%d1        //get 3rd dest
    364364        cmpb    %d0,%d1                 //cmp 1st dest with 3rd dest
    365365        beq     op2_com                 //if equal, continue bugfix
    366         bfextu  CMDREG2B(%a6){#6:#3},%d1        //get 2nd dest 
     366        bfextu  CMDREG2B(%a6){#6:#3},%d1        //get 2nd dest
    367367        cmpb    %d0,%d1                 //cmp 1st dest with 2nd dest
    368368        bne     fix_done                //if the reg checks fail, exit
    369369//
    370370// We have the case in which a conflict exists between the cu src or
    371 // dest and the dest of the xu.  We must clear the instruction in 
     371// dest and the dest of the xu.  We must clear the instruction in
    372372// the cu and restore the state, allowing the instruction in the
    373373// xu to complete.  Remember, the instruction in the nu
     
    379379//
    380380//      Items saved from the stack:
    381 //     
     381//
    382382//              $3c stag     - L_SCR1
    383383//              $40 cmdreg1b - L_SCR2
     
    389389//
    390390op2_xu:
    391         movel   STAG(%a6),L_SCR1(%a6)   
    392         movel   CMDREG1B(%a6),L_SCR2(%a6)       
    393         movel   DTAG(%a6),L_SCR3(%a6)   
     391        movel   STAG(%a6),L_SCR1(%a6)
     392        movel   CMDREG1B(%a6),L_SCR2(%a6)
     393        movel   DTAG(%a6),L_SCR3(%a6)
    394394        andil   #0xe0000000,L_SCR3(%a6)
    395395        moveb   #0,CU_SAVEPC(%a6)
     
    402402//
    403403// Check if the instruction which just completed was exceptional.
    404 // 
     404//
    405405        cmpw    #0x4060,(%a7)
    406406        beq     op2_xb
    407 // 
     407//
    408408// It is necessary to isolate the result of the instruction in the
    409409// xu if it is to fp0 - fp3 and write that value to the USER_FPn
    410 // locations on the stack.  The correct destination register is in 
     410// locations on the stack.  The correct destination register is in
    411411// cmdreg2b.
    412412//
     
    461461        movew   #0x43FF,ETEMP_EX(%a6)   //to double +max
    462462        bra     finish
    463 case2: 
     463case2:
    464464        cmpw    #0xC07F,ETEMP_EX(%a6)   //single -max
    465465        bnes    case3
    466466        movew   #0xC3FF,ETEMP_EX(%a6)   //to double -max
    467467        bra     finish
    468 case3: 
     468case3:
    469469        cmpw    #0x3F80,ETEMP_EX(%a6)   //single +min
    470470        bnes    case4
     
    482482//
    483483// You should replace the jump to fpsp_fmt_error with a jump
    484 // to the entry point used to kill a process. 
     484// to the entry point used to kill a process.
    485485//
    486486op2_xb:
  • c/src/lib/libcpu/m68k/m68040/fpsp/decbin.S

    r06731d6 r42e243e  
    6363//
    6464//      Clean up and return.  Check if the final mul or div resulted
    65 //      in an inex2 exception.  If so, set inex1 in the fpsr and 
     65//      in an inex2 exception.  If so, set inex1 in the fpsr and
    6666//      check if the inex1 exception is enabled.  If so, set d7 upper
    6767//      word to $0100.  This will signal unimp.sa that an enabled inex1
    6868//      exception occurred.  Unimp will fix the stack.
    69 //     
     69//
    7070
    7171//              Copyright (C) Motorola, Inc. 1990
    7272//                      All Rights Reserved
    7373//
    74 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    75 //      The copyright notice above does not evidence any 
     74//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     75//      The copyright notice above does not evidence any
    7676//      actual or intended publication of such source code.
    7777
     
    110110//
    111111        .set    ESTRT,4
    112         .set    EDIGITS,2       // 
     112        .set    EDIGITS,2       //
    113113//
    114114// Constants in single precision
     
    227227        cmpl    #2,%d1          //test for last lw
    228228        ble     loadlw          //if not, get last one
    229        
     229
    230230//
    231231//  Check the sign of the mant and make the value in fp0 the same sign.
     
    235235        beq     ap_st_z         //if clear, go to append/strip zeros
    236236        fnegx   %fp0            //if set, negate fp0
    237        
     237
    238238//
    239239// Append/strip zeros:
     
    410410// Pwrten calculates the exponent factor in the selected rounding mode
    411411// according to the following table:
    412 //     
     412//
    413413//      Sign of Mant  Sign of Exp  Rounding Mode  PWRTEN Rounding Mode
    414414//
     
    498498//
    499499end_dec:
    500         fmovel  %FPSR,%d0               //get status register   
     500        fmovel  %FPSR,%d0               //get status register
    501501        bclrl   #inex2_bit+8,%d0        //test for inex2 and clear it
    502502        fmovel  %d0,%FPSR               //return status reg w/o inex2
  • c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S

    r06731d6 r42e243e  
    77// to be performed is determined from the lower 7 bits of the
    88// extension word (except in the case of fmovecr and fsincos).
    9 // The opcode and tag bits form an index into a jump table in 
    10 // tbldo.sa.  Cases of zero, infinity and NaN are handled in 
     9// The opcode and tag bits form an index into a jump table in
     10// tbldo.sa.  Cases of zero, infinity and NaN are handled in
    1111// do_func by forcing the default result.  Normalized and
    1212// denormalized (there are no unnormalized numbers at this
    13 // point) are passed onto the emulation code. 
     13// point) are passed onto the emulation code.
    1414//
    1515// CMDREG1B and STAG are extracted from the fsave frame
     
    2525//                      All Rights Reserved
    2626//
    27 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    28 //      The copyright notice above does not evidence any 
     27//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     28//      The copyright notice above does not evidence any
    2929//      actual or intended publication of such source code.
    3030
     
    7171//
    7272        bfextu  CMDREG1B(%a6){#0:#6},%d0 //get opclass and src fields
    73         cmpil   #0x17,%d0               //if op class and size fields are $17, 
     73        cmpil   #0x17,%d0               //if op class and size fields are $17,
    7474//                              ;it is FMOVECR; if not, continue
    7575        bnes    not_fmovecr
     
    7979        movew   CMDREG1B(%a6),%d0
    8080        andl    #0x7F,%d0
    81         cmpil   #0x38,%d0               //if the extension is >= $38, 
     81        cmpil   #0x38,%d0               //if the extension is >= $38,
    8282        bge     serror          //it is illegal
    8383        bfextu  STAG(%a6){#0:#3},%d1
     
    114114        bra     t_inx2          //now, set the inx for the next inst
    115115//
    116 // Load a signed zero to fp0; do not set inex2/ainex 
     116// Load a signed zero to fp0; do not set inex2/ainex
    117117//
    118118        .global szero
     
    122122        bra     ld_pzero        //load positive zero
    123123//
    124 // Load a signed infinity to fp0; do not set inex2/ainex 
     124// Load a signed infinity to fp0; do not set inex2/ainex
    125125//
    126126        .global sinf
     
    130130        bra     ld_pinf
    131131//
    132 // Load a signed one to fp0; do not set inex2/ainex 
     132// Load a signed one to fp0; do not set inex2/ainex
    133133//
    134134        .global sone
     
    138138        bra     ld_pone
    139139//
    140 // Load a signed pi/2 to fp0; do not set inex2/ainex 
     140// Load a signed pi/2 to fp0; do not set inex2/ainex
    141141//
    142142        .global spi_2
     
    163163        bra     ld_pinf
    164164//
    165 //      FLOGNP1 
     165//      FLOGNP1
    166166//
    167167        .global sslognp1
     
    169169        fmovemx (%a0),%fp0-%fp0
    170170        fcmpb   #-1,%fp0
    171         fbgt    slognp1         
     171        fbgt    slognp1
    172172        fbeq    t_dz2           //if = -1, divide by zero exception
    173173        fmovel  #0,%FPSR                //clr N flag
     
    189189        .global sslogn
    190190sslogn:
    191         btstb   #sign_bit,LOCAL_EX(%a0) 
     191        btstb   #sign_bit,LOCAL_EX(%a0)
    192192        bne     t_operr         //take care of operands < 0
    193193        cmpiw   #0x3fff,LOCAL_EX(%a0) //test for 1.0 input
     
    202202        .global sslognd
    203203sslognd:
    204         btstb   #sign_bit,LOCAL_EX(%a0) 
     204        btstb   #sign_bit,LOCAL_EX(%a0)
    205205        beq     slognd
    206206        bra     t_operr         //take care of operands < 0
     
    224224        .global sslog10d
    225225sslog10d:
    226         btstb   #sign_bit,LOCAL_EX(%a0) 
     226        btstb   #sign_bit,LOCAL_EX(%a0)
    227227        beq     slog10d
    228228        bra     t_operr         //take care of operands < 0
     
    246246        .global sslog2d
    247247sslog2d:
    248         btstb   #sign_bit,LOCAL_EX(%a0) 
     248        btstb   #sign_bit,LOCAL_EX(%a0)
    249249        beq     slog2d
    250250        bra     t_operr         //take care of operands < 0
     
    313313        beq     ld_pzero        //if pos then load +0
    314314        bra     ld_mzero        //else neg load -0
    315        
     315
    316316smod_fpn:
    317317        moveb   ETEMP(%a6),%d1  //get sign of src op
     
    330330        fmovex FPTEMP(%a6),%fp0 //return dest to fp0
    331331        rts
    332                
     332
    333333//
    334334//      FREM
     
    375375        movel   (%a1,%d1.w*4),%a1
    376376        jmp     (%a1)
    377        
     377
    378378srem_snan:
    379379        bra     src_nan
     
    393393        beq     ld_pzero        //if pos then load +0
    394394        bra     ld_mzero        //else neg load -0
    395        
     395
    396396srem_fpn:
    397397        moveb   ETEMP(%a6),%d1  //get sign of src op
     
    501501        bra     src_nan
    502502//
    503 // This code forces default values for the zero, inf, and nan cases 
     503// This code forces default values for the zero, inf, and nan cases
    504504// in the transcendentals code.  The CC bits must be set in the
    505505// stacked FPSR to be correctly reported.
  • c/src/lib/libcpu/m68k/m68040/fpsp/gen_except.S

    r06731d6 r42e243e  
    55//
    66//      gen_except --- FPSP routine to detect reportable exceptions
    7 //     
     7//
    88//      This routine compares the exception enable byte of the
    99//      user_fpcr on the stack with the exception status byte
    10 //      of the user_fpsr. 
     10//      of the user_fpsr.
    1111//
    1212//      Any routine which may report an exceptions must load
     
    2626//      Note: The IEEE standard specifies that inex2 is to be
    2727//      reported if ovfl occurs and the ovfl enable bit is not
    28 //      set but the inex2 enable bit is. 
     28//      set but the inex2 enable bit is.
    2929//
    3030//
     
    3232//                      All Rights Reserved
    3333//
    34 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    35 //      The copyright notice above does not evidence any 
     34//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     35//      The copyright notice above does not evidence any
    3636//      actual or intended publication of such source code.
    3737
     
    7373        movel   ETEMP_EX(%a6),ETEMP_EX(%a1) //copy etemp from unimp
    7474        movel   ETEMP_HI(%a6),ETEMP_HI(%a1) //frame to busy frame
    75         movel   ETEMP_LO(%a6),ETEMP_LO(%a1) 
     75        movel   ETEMP_LO(%a6),ETEMP_LO(%a1)
    7676        movel   CMDREG1B(%a6),CMDREG1B(%a1) //set inst in frame to unimp
    7777        movel   CMDREG1B(%a6),%d0               //fix cmd1b to make it
    7878        andl    #0x03c30000,%d0         //work for cmd3b
    7979        bfextu  CMDREG1B(%a6){#13:#1},%d1       //extract bit 2
    80         lsll    #5,%d1                 
     80        lsll    #5,%d1
    8181        swap    %d1
    8282        orl     %d1,%d0                 //put it in the right place
     
    8989// Or in the FPSR from the emulation with the USER_FPSR on the stack.
    9090//
    91         fmovel  %FPSR,%d0               
     91        fmovel  %FPSR,%d0
    9292        orl     %d0,USER_FPSR(%a6)
    9393        movel   USER_FPSR(%a6),FPSR_SHADOW(%a1) //set exc bits
     
    111111        bnel    fpsp_fmt_error          //if not $28 or $30
    112112        leal    UNIMP_41_SIZE+LOCAL_SIZE(%a7),%a1
    113        
     113
    114114unimp_con:
    115115//
     
    120120// Or in the FPSR from the emulation with the USER_FPSR on the stack.
    121121//
    122         fmovel  %FPSR,%d0               
     122        fmovel  %FPSR,%d0
    123123        orl     %d0,USER_FPSR(%a6)
    124124        bra     do_clean
     
    126126//
    127127// Frame is idle, so check for exceptions reported through
    128 // USER_FPSR and set the unimp frame accordingly. 
     128// USER_FPSR and set the unimp frame accordingly.
    129129// A7 must be incremented to the point before the
    130130// idle fsave vector to the unimp vector.
    131131//
    132        
     132
    133133do_check:
    134134        addl    #4,%a7                  //point A7 back to unimp frame
     
    136136// Or in the FPSR from the emulation with the USER_FPSR on the stack.
    137137//
    138         fmovel  %FPSR,%d0               
     138        fmovel  %FPSR,%d0
    139139        orl     %d0,USER_FPSR(%a6)
    140140//
     
    168168        bra     do_clean
    169169//
    170 // The typical work to be done to the unimp frame to report an 
     170// The typical work to be done to the unimp frame to report an
    171171// exception is to set the E1/E3 byte and clr the U flag.
    172 // commonE1 does this for E1 exceptions, which are snan, 
    173 // operr, and dz.  commonE3 does this for E3 exceptions, which 
     172// commonE1 does this for E1 exceptions, which are snan,
     173// operr, and dz.  commonE3 does this for E3 exceptions, which
    174174// are inex2 and inex1, and also clears the E1 exception bit
    175175// left over from the unimp exception.
     
    189189unsE3:
    190190        tstb    RES_FLG(%a6)
    191         bnes    unsE3_0 
     191        bnes    unsE3_0
    192192unsE3_1:
    193193        bsetb   #E3,E_BYTE(%a6)         //set E3 flag
     
    197197        andl    #0x03c30000,%d0         //work for cmd3b
    198198        bfextu  CMDREG1B(%a6){#13:#1},%d1       //extract bit 2
    199         lsll    #5,%d1                 
     199        lsll    #5,%d1
    200200        swap    %d1
    201201        orl     %d1,%d0                 //put it in the right place
     
    221221        bras    ovfl_unfl               //go to unfl_ovfl to determine if
    222222//                                      ;it is an unsupp or unimp exc
    223        
    224 // No exceptions are to be reported.  If the instruction was 
     223
     224// No exceptions are to be reported.  If the instruction was
    225225// unimplemented, no FPU restore is necessary.  If it was
    226226// unsupported, we must perform the restore.
     
    246246// Unimplemented Instruction Handler:
    247247// Ovfl:
    248 //   Only scosh, setox, ssinh, stwotox, and scale can set overflow in 
     248//   Only scosh, setox, ssinh, stwotox, and scale can set overflow in
    249249//   this manner.
    250250// Unfl:
    251251//   Stwotox, setox, and scale can set underflow in this manner.
    252252//   Any of the other Library Routines such that f(x)=x in which
    253 //   x is an extended denorm can report an underflow exception. 
    254 //   It is the responsibility of the exception-causing exception 
     253//   x is an extended denorm can report an underflow exception.
     254//   It is the responsibility of the exception-causing exception
    255255//   to make sure that WBTEMP is correct.
    256256//
     
    309309        andl    #0x03c30000,%d0         //work for cmd3b
    310310        bfextu  CMDREG1B(%a6){#13:#1},%d1       //extract bit 2
    311         lsll    #5,%d1                 
     311        lsll    #5,%d1
    312312        swap    %d1
    313313        orl     %d1,%d0                 //put it in the right place
     
    321321// Check if the frame to be restored is busy or unimp.
    322322//** NOTE *** Bug fix for errata (0d43b #3)
    323 // If the frame is unimp, we must create a busy frame to 
     323// If the frame is unimp, we must create a busy frame to
    324324// fix the bug with the nmnexc bits in cases in which they
    325325// are set by a previous instruction and not cleared by
    326 // the save. The frame will be unimp only if the final 
     326// the save. The frame will be unimp only if the final
    327327// instruction in an emulation routine caused the exception
    328328// by doing an fmove <ea>,fp0.  The exception operand, in
     
    365365        movel   USER_FPSR(%a6),FPSR_SHADOW(%a1) //set exc bits
    366366        orl     #sx_mask,E_BYTE(%a1)
    367        
     367
    368368do_restore:
    369369        moveml  USER_DA(%a6),%d0-%d1/%a0-%a1
     
    377377        unlk    %a6
    378378//
    379 // If trace mode enabled, then go to trace handler.  This handler 
    380 // cannot have any fp instructions.  If there are fp inst's and an 
    381 // exception has been restored into the machine then the exception 
    382 // will occur upon execution of the fp inst.  This is not desirable 
     379// If trace mode enabled, then go to trace handler.  This handler
     380// cannot have any fp instructions.  If there are fp inst's and an
     381// exception has been restored into the machine then the exception
     382// will occur upon execution of the fp inst.  This is not desirable
    383383// in the kernel (supervisor mode).  See MC68040 manual Section 9.3.8.
    384384//
     
    439439        movel   #0x40280000,-(%sp)
    440440        frestore (%sp)+
    441         unlk    %a5     
     441        unlk    %a5
    442442        rts
    443443
    444444frame_41:
    445445        tstb    1(%sp)          // check to see if idle
    446         bne     notidle 
     446        bne     notidle
    447447idle41:
    448448        clrl    (%sp)           // get rid of old fsave frame
     
    454454        movel   #0x41300000,-(%sp)
    455455        frestore (%sp)+
    456         unlk    %a5     
     456        unlk    %a5
    457457        rts
    458458
    459459notidle:
    460         bclrb   #etemp15_bit,-40(%a5) 
     460        bclrb   #etemp15_bit,-40(%a5)
    461461        frestore (%sp)+
    462         unlk    %a5     
     462        unlk    %a5
    463463        rts
    464464
    465465nofix:
    466466        frestore (%sp)+
    467         unlk    %a5     
     467        unlk    %a5
    468468        rts
    469469
  • c/src/lib/libcpu/m68k/m68040/fpsp/get_op.S

    r06731d6 r42e243e  
    1919// - For unnormalized numbers (opclass 0, 2, or 3) the
    2020// number(s) is normalized and the operand type tag is updated.
    21 //             
     21//
    2222// - For a packed number (opclass 2) the number is unpacked and the
    2323// operand type tag is updated.
     
    4444// a normalized number in the source and the instruction is
    4545// successful.
    46 //             
     46//
    4747// Next consider if in the process of normalizing the un-
    4848// normalized number it becomes a denormalized number.  The
     
    5757//                      All Rights Reserved
    5858//
    59 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    60 //      The copyright notice above does not evidence any 
     59//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     60//      The copyright notice above does not evidence any
    6161//      actual or intended publication of such source code.
    6262
     
    197197uni_getop:
    198198        bfextu  CMDREG1B(%a6){#0:#6},%d0 //get opclass and src fields
    199         cmpil   #0x17,%d0               //if op class and size fields are $17, 
     199        cmpil   #0x17,%d0               //if op class and size fields are $17,
    200200//                              ;it is FMOVECR; if not, continue
    201201//
     
    229229        andiw   #0x7fff,%d0     //mask sign, check if exp = 0000
    230230        beqs    src_op_ck       //if denorm then check source op.
    231 //                              ;denorms are taken care of in res_func 
     231//                              ;denorms are taken care of in res_func
    232232//                              ;(unsupp) or do_func (unimp)
    233233//                              ;else unnorm fall through
    234234        leal    FPTEMP(%a6),%a0 //point a0 to dop - used in mk_norm
    235235        bsr     mk_norm         //go normalize - mk_norm returns:
    236 //                              ;L_SCR1{7:5} = operand tag 
     236//                              ;L_SCR1{7:5} = operand tag
    237237//                              ;       (000 = norm, 100 = denorm)
    238 //                              ;L_SCR1{4} = fpte15 or ete15 
     238//                              ;L_SCR1{4} = fpte15 or ete15
    239239//                              ;       0 = exp >  $3fff
    240240//                              ;       1 = exp <= $3fff
    241 //                              ;and puts the normalized num back 
     241//                              ;and puts the normalized num back
    242242//                              ;on the fsave stack
    243243//
    244         moveb L_SCR1(%a6),DTAG(%a6) //write the new tag & fpte15 
    245 //                              ;to the fsave stack and fall 
     244        moveb L_SCR1(%a6),DTAG(%a6) //write the new tag & fpte15
     245//                              ;to the fsave stack and fall
    246246//                              ;through to check source operand
    247247//
     
    258258        movew   ETEMP_EX(%a6),%d0 //get source exponent
    259259        andiw   #0x7fff,%d0     //mask sign, check if exp = 0000
    260         beq     end_getop       //if denorm then exit, denorms are 
     260        beq     end_getop       //if denorm then exit, denorms are
    261261//                              ;handled in do_func
    262262        leal    ETEMP(%a6),%a0  //point a0 to sop - used in mk_norm
    263263        bsr     mk_norm         //go normalize - mk_norm returns:
    264 //                              ;L_SCR1{7:5} = operand tag 
     264//                              ;L_SCR1{7:5} = operand tag
    265265//                              ;       (000 = norm, 100 = denorm)
    266 //                              ;L_SCR1{4} = fpte15 or ete15 
     266//                              ;L_SCR1{4} = fpte15 or ete15
    267267//                              ;       0 = exp >  $3fff
    268268//                              ;       1 = exp <= $3fff
    269 //                              ;and puts the normalized num back 
     269//                              ;and puts the normalized num back
    270270//                              ;on the fsave stack
    271271//
    272         moveb   L_SCR1(%a6),STAG(%a6) //write the new tag & ete15 
     272        moveb   L_SCR1(%a6),STAG(%a6) //write the new tag & ete15
    273273        rts                     //end_getop
    274274
     
    288288common:
    289289        btstb   #sign_bit,ETEMP_EX(%a6) //grab sign bit of mantissa
    290         beqs    pos     
     290        beqs    pos
    291291        bset    #15,%d1         //set sign bit because it is negative
    292292pos:
     
    300300//                              ;this is needed to fix unsupp data stack
    301301        leal    ETEMP(%a6),%a0  //point a0 to sop
    302        
     302
    303303        bsr     mk_norm         //convert sgl/dbl denorm to norm
    304304        moveb   L_SCR1(%a6),STAG(%a6) //put tag into source tag reg - d0
     
    309309//
    310310pack_source:
    311         movel   FPTEMP_LO(%a6),ETEMP(%a6)       //write ms part of packed 
     311        movel   FPTEMP_LO(%a6),ETEMP(%a6)       //write ms part of packed
    312312//                              ;number to etemp slot
    313313        bsr     chk_dy_mo       //set dyadic/monadic flag
     
    328328        bne     dst_ex_dnrm     //else, handle the unnorm or ext denorm
    329329//
    330 // Dest is not denormalized.  Check for norm, and set fpte15 
     330// Dest is not denormalized.  Check for norm, and set fpte15
    331331// accordingly.
    332332//
     
    360360//
    361361chk_dy_mo:
    362         movew   CMDREG1B(%a6),%d0       
     362        movew   CMDREG1B(%a6),%d0
    363363        btstl   #5,%d0          //testing extension command word
    364364        beqs    set_mon         //if bit 5 = 0 then monadic
     
    409409//      L_SCR1{4}   = fpte15 or ete15 (0 = exp > $3fff, 1 = exp <=$3fff)
    410410//      the normalized operand is placed back on the fsave stack
    411 mk_norm:       
     411mk_norm:
    412412        clrl    L_SCR1(%a6)
    413413        bclrb   #sign_bit,LOCAL_EX(%a0)
     
    429429        bgts    end_mk          //   fpte15/ete15 already set to 0
    430430        bsetb   #4,L_SCR1(%a6)  //else set fpte15/ete15 to 1
    431 //                              ;calling routine actually sets the 
    432 //                              ;value on the stack (along with the 
    433 //                              ;tag), since this routine doesn't 
     431//                              ;calling routine actually sets the
     432//                              ;value on the stack (along with the
     433//                              ;tag), since this routine doesn't
    434434//                              ;know if it should set ete15 or fpte15
    435 //                              ;ie, it doesn't know if this is the 
     435//                              ;ie, it doesn't know if this is the
    436436//                              ;src op or dest op.
    437437end_mk:
     
    458458uns_opx:
    459459        bsr     nrm_zero        //normalize the number
    460         btstb   #7,LOCAL_HI(%a0)        //check if integer bit (j-bit) is set 
     460        btstb   #7,LOCAL_HI(%a0)        //check if integer bit (j-bit) is set
    461461        beqs    uns_den         //if clear then now have a denorm
    462462uns_nrm:
     
    471471uni_inst:
    472472        bsr     nrm_zero
    473         btstb   #7,LOCAL_HI(%a0)        //check if integer bit (j-bit) is set 
     473        btstb   #7,LOCAL_HI(%a0)        //check if integer bit (j-bit) is set
    474474        beqs    uni_den         //if clear then now have a denorm
    475475uni_nrm:
     
    483483//      Decimal to binary conversion
    484484//
    485 // Special cases of inf and NaNs are completed outside of decbin. 
     485// Special cases of inf and NaNs are completed outside of decbin.
    486486// If the input is an snan, the snan bit is not set.
    487 // 
     487//
    488488// input:
    489489//      ETEMP(a6)       - points to packed decimal string in memory
     
    613613finish:
    614614        movew   CMDREG1B(%a6),%d0       //get the command word
    615         andw    #0xfbff,%d0     //change the source specifier field to 
     615        andw    #0xfbff,%d0     //change the source specifier field to
    616616//                              ;extended (was packed).
    617617        movew   %d0,CMDREG1B(%a6)       //write command word back to fsave stack
    618 //                              ;we need to do this so the 040 will 
    619 //                              ;re-execute the inst. without taking 
     618//                              ;we need to do this so the 040 will
     619//                              ;re-execute the inst. without taking
    620620//                              ;another packed trap.
    621621
    622622fix_stag:
    623 //Converted result is now in etemp on fsave stack, now set the source 
    624 //tag (stag) 
     623//Converted result is now in etemp on fsave stack, now set the source
     624//tag (stag)
    625625//      if (ete =$7fff) then INF or NAN
    626626//              if (etemp = $x.0----0) then
     
    635635//
    636636// Note also that the etemp_15 bit (just right of the stag) must
    637 // be set accordingly. 
     637// be set accordingly.
    638638//
    639639        movew           ETEMP_EX(%a6),%d1
     
    654654        rts
    655655z_or_nrm:
    656         tstw            %d1 
     656        tstw            %d1
    657657        bnes            is_nrm
    658658is_zro:
     
    673673end_fix:
    674674        rts
    675  
     675
    676676end_get:
    677677        rts
  • c/src/lib/libcpu/m68k/m68040/fpsp/kernel_ex.S

    r06731d6 r42e243e  
    22//      $Id$
    33//
    4 //      kernel_ex.sa 3.3 12/19/90 
    5 //
    6 // This file contains routines to force exception status in the 
     4//      kernel_ex.sa 3.3 12/19/90
     5//
     6// This file contains routines to force exception status in the
    77// fpu for exceptional cases detected or reported within the
    88// transcendental functions.  Typically, the t_xx routine will
    99// set the appropriate bits in the USER_FPSR word on the stack.
    1010// The bits are tested in gen_except.sa to determine if an exceptional
    11 // situation needs to be created on return from the FPSP. 
     11// situation needs to be created on return from the FPSP.
    1212//
    1313
     
    1515//                      All Rights Reserved
    1616//
    17 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    18 //      The copyright notice above does not evidence any 
     17//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     18//      The copyright notice above does not evidence any
    1919//      actual or intended publication of such source code.
    2020
     
    5252//      if dz trap disabled
    5353//              store properly signed inf (use sign of etemp) into fp0
    54 //              set FPSR exception status dz bit, condition code 
     54//              set FPSR exception status dz bit, condition code
    5555//              inf bit, and accrued dz bit
    5656//              return
     
    6464//
    6565// t_dz2 is used by monadic functions such as flogn (from do_func).
    66 // t_dz is used by monadic functions such as satanh (from the 
     66// t_dz is used by monadic functions such as satanh (from the
    6767// transcendental function).
    6868//
     
    107107//
    108108//      if (operr trap disabled)
    109 //              set FPSR exception status operr bit, condition code 
     109//              set FPSR exception status operr bit, condition code
    110110//              nan bit; Store default NAN into fp0
    111111//              frestore the frame into the machine (done by unimp_hd)
    112 //     
     112//
    113113//      else (operr trap enabled)
    114114//              set FPSR exception status operr bit, accrued operr bit
     
    162162unfl_dis:
    163163        bfextu  FPCR_MODE(%a6){#0:#2},%d0       //get round precision
    164        
     164
    165165        bclrb   #sign_bit,LOCAL_EX(%a0)
    166166        sne     LOCAL_SGN(%a0)          //convert to internal ext format
     
    168168        bsr     unf_sub                 //returns IEEE result at a0
    169169//                                      ;and sets FPSR_CC accordingly
    170        
     170
    171171        bfclr   LOCAL_SGN(%a0){#0:#8}   //convert back to IEEE ext format
    172172        beqs    unfl_fin
     
    178178        fmovemx (%a0),%fp0-%fp0         //store result in fp0
    179179        rts
    180        
     180
    181181
    182182//
     
    283283//
    284284// Determine if the destination nan is signalling or non-signalling,
    285 // and set the FPSR bits accordingly.  See the MC68040 User's Manual 
     285// and set the FPSR bits accordingly.  See the MC68040 User's Manual
    286286// section 3.2.2.5 NOT-A-NUMBERS.
    287287//
     
    291291        bsetb   #neg_bit,FPSR_CC(%a6)   //set N bit
    292292dst_pos:
    293         btstb   #signan_bit,FPTEMP_HI(%a6) //check if signalling 
     293        btstb   #signan_bit,FPTEMP_HI(%a6) //check if signalling
    294294        beqs    dst_snan                //branch if signalling
    295295
     
    303303        cmpib   #0x60,%d0
    304304        bnes    no_snan
    305         btstb   #signan_bit,ETEMP_HI(%a6) //check if signalling 
     305        btstb   #signan_bit,ETEMP_HI(%a6) //check if signalling
    306306        bnes    no_snan
    307307        orl     #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP
    308308no_snan:
    309         rts     
     309        rts
    310310
    311311dst_snan:
    312         btstb   #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled 
     312        btstb   #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled
    313313        beqs    dst_dis                 //branch if disabled
    314314
     
    319319
    320320dst_dis:
    321         bsetb   #signan_bit,FPTEMP_HI(%a6) //set SNAN bit in sop 
     321        bsetb   #signan_bit,FPTEMP_HI(%a6) //set SNAN bit in sop
    322322        fmovel  %d1,%fpcr                       //restore user's rmode/prec
    323         fmovex FPTEMP(%a6),%fp0         //load non-sign. nan 
     323        fmovex FPTEMP(%a6),%fp0         //load non-sign. nan
    324324        orl     #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP
    325325        rts
     
    329329//
    330330// Determine if the source nan is signalling or non-signalling,
    331 // and set the FPSR bits accordingly.  See the MC68040 User's Manual 
     331// and set the FPSR bits accordingly.  See the MC68040 User's Manual
    332332// section 3.2.2.5 NOT-A-NUMBERS.
    333333//
     
    337337        bsetb   #neg_bit,FPSR_CC(%a6)   //set N bit
    338338src_pos:
    339         btstb   #signan_bit,ETEMP_HI(%a6) //check if signalling 
     339        btstb   #signan_bit,ETEMP_HI(%a6) //check if signalling
    340340        beqs    src_snan                //branch if signalling
    341341        fmovel  %d1,%fpcr                       //restore user's rmode/prec
    342342        fmovex ETEMP(%a6),%fp0          //return the non-signalling nan
    343         rts     
     343        rts
    344344
    345345src_snan:
    346         btstb   #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled 
     346        btstb   #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled
    347347        beqs    src_dis                 //branch if disabled
    348         bsetb   #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop 
     348        bsetb   #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop
    349349        orb     #norm_tag,DTAG(%a6)     //set up dtag for norm
    350350        orb     #nan_tag,STAG(%a6)      //set up stag for nan
     
    354354
    355355src_dis:
    356         bsetb   #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop 
     356        bsetb   #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop
    357357        fmovel  %d1,%fpcr                       //restore user's rmode/prec
    358         fmovex ETEMP(%a6),%fp0          //load non-sign. nan 
     358        fmovex ETEMP(%a6),%fp0          //load non-sign. nan
    359359        orl     #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP
    360360        rts
     
    370370//
    371371// Entry point for scale with extended denorm.  The function does
    372 // not set inex2, aunfl, or ainex. 
     372// not set inex2, aunfl, or ainex.
    373373//
    374374t_resdnrm:
     
    405405        beqs    xdep
    406406        bsetb   #sign_bit,LOCAL_EX(%a0)
    407 xdep:   
     407xdep:
    408408        bfclr   STAG(%a6){#5:#3}                //clear wbtm66,wbtm1,wbtm0
    409409        bsetb   #wbtemp15_bit,WB_BYTE(%a6) //set wbtemp15
     
    442442        .global t_avoid_unsupp
    443443t_avoid_unsupp:
    444         link    %a2,#-LOCAL_SIZE                //so that a2 fpsp.h negative 
     444        link    %a2,#-LOCAL_SIZE                //so that a2 fpsp.h negative
    445445//                                      ;offsets may be used
    446446        fsave   -(%a7)
  • c/src/lib/libcpu/m68k/m68040/fpsp/res_func.S

    r06731d6 r42e243e  
    1111//
    1212// For packed move out (fmove.p fpm,<ea>) the operation is
    13 // completed here; data is packed and moved to user memory. 
     13// completed here; data is packed and moved to user memory.
    1414// The stack is restored to the 040 only in the case of a
    1515// reportable exception in the conversion.
     
    1919//                      All Rights Reserved
    2020//
    21 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    22 //      The copyright notice above does not evidence any 
     21//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     22//      The copyright notice above does not evidence any
    2323//      actual or intended publication of such source code.
    2424
     
    103103        andil   #0x7f,%d0                       //strip to only command word
    104104//
    105 // At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and 
     105// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
    106106// fdsqrt are possible.
    107107// For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
     
    146146cu_ntn:
    147147        orl     #nan_mask,USER_FPSR(%a6)
    148         movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for 
     148        movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for
    149149//                                              ;snan handler
    150150
     
    209209        movel   #2,%d0                  //set up the size for denorm
    210210        movew   LOCAL_EX(%a0),%d1               //compare exponent to double threshold
    211         andw    #0x7fff,%d1     
     211        andw    #0x7fff,%d1
    212212        cmpw    #0x3c01,%d1
    213213        bls     cu_nunfl
     
    362362mon_dnrm:
    363363//
    364 // At this point, check for the cases in which normalizing the 
     364// At this point, check for the cases in which normalizing the
    365365// denorm produces incorrect results.
    366366//
     
    377377        andil   #0x7f,%d0                       //strip to only command word
    378378//
    379 // At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and 
     379// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
    380380// fdsqrt are possible.
    381381// For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
     
    385385        bnes    nrm_src         //weed out fsqrt instructions
    386386        st      CU_ONLY(%a6)    //set cu-only inst flag
    387         bra     cu_dnrm         //fmove, fabs, fneg, ftst 
     387        bra     cu_dnrm         //fmove, fabs, fneg, ftst
    388388//                              ;cases go to cu_dnrm
    389389nrm_src:
    390390        bclrb   #sign_bit,LOCAL_EX(%a0)
    391391        sne     LOCAL_SGN(%a0)
    392         bsr     nrm_set         //normalize number (exponent will go 
     392        bsr     nrm_set         //normalize number (exponent will go
    393393//                              ; negative)
    394394        bclrb   #sign_bit,LOCAL_EX(%a0) //get rid of false sign
     
    416416//
    417417// cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and
    418 // ftst) completely in software without an frestore to the 040. 
     418// ftst) completely in software without an frestore to the 040.
    419419//
    420420cu_dnrm:
     
    449449cu_dtn:
    450450        orl     #nan_mask,USER_FPSR(%a6)
    451         movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for 
     451        movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for
    452452//                                              ;snan handler
    453453        rts
     
    528528//
    529529// The precision is extended, so the result in etemp is correct.
    530 // Simply set unfl (not inex2 or aunfl) and write the result to 
     530// Simply set unfl (not inex2 or aunfl) and write the result to
    531531// the correct fp register.
    532532cu_wrexd:
     
    600600        orl     #unfinx_mask,USER_FPSR(%a6)
    601601        bra     wr_etemp
    602        
     602
    603603//
    604604// This code checks for 16-bit overflow conditions on dyadic
     
    616616//
    617617// The wrap-around condition occurs for add, sub, div, and cmp
    618 // when 
     618// when
    619619//
    620620//      abs(dest_exp - src_exp) >= $8000
     
    630630// No frestore is done unless an exception is to be reported.
    631631//
    632 // For fadd: 
     632// For fadd:
    633633//      if(sign_of(dest) != sign_of(src))
    634634//              replace exponent of src with $3fff (keep sign)
     
    692692        beq     wrap_cmp
    693693//
    694 // Inst is fdiv. 
     694// Inst is fdiv.
    695695//
    696696wrap_div:
    697         cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm, 
     697        cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm,
    698698        beq     fix_stk          //restore to fpu
    699699//
     
    725725ckinf_nd:
    726726        moveb   DTAG(%a6),%d0           //check destination tag for inf or nan
    727 ck_in_com:     
     727ck_in_com:
    728728        andib   #0x60,%d0                       //isolate tag bits
    729729        cmpb    #0x40,%d0                       //is it inf?
     
    758758        st      WBTEMP_SGN(%a6)
    759759//
    760 // This code handles the case of the instruction resulting in 
     760// This code handles the case of the instruction resulting in
    761761// an overflow condition.
    762762//
     
    780780frcovf_rnd:
    781781
    782 // The 881/882 does not set inex2 for the following case, so the 
     782// The 881/882 does not set inex2 for the following case, so the
    783783// line is commented out to be compatible with 881/882
    784784//      tst.b   %d0
     
    788788//frcovf_x:
    789789        bsrl    ovf_res                 //get correct result based on
    790 //                                      ;round precision/mode.  This 
     790//                                      ;round precision/mode.  This
    791791//                                      ;sets FPSR_CC correctly
    792792//                                      ;returns in external format
     
    799799//
    800800wrap_add:
    801         cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm, 
     801        cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm,
    802802        beq     fix_stk          //restore to fpu
    803803//
     
    967967// round routine.)
    968968//
    969         orl     #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) 
     969        orl     #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
    970970        clrl    4(%a0)
    971971        bra     frcfpnr
     
    974974//
    975975wrap_sub:
    976         cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm, 
     976        cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm,
    977977        beq     fix_stk          //restore to fpu
    978978//
     
    11481148// round routine.)
    11491149//
    1150         orl     #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) 
     1150        orl     #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
    11511151        clrl    4(%a0)
    11521152        bra     frcfpnr
     
    11551155//
    11561156wrap_cmp:
    1157         cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm, 
     1157        cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm,
    11581158        beq     fix_stk          //restore to fpu
    11591159//
     
    11931193//
    11941194wrap_mul:
    1195         cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm, 
     1195        cmpb    #0xff,DNRM_FLG(%a6) //if both ops denorm,
    11961196        beq     force_unf       //force an underflow (really!)
    11971197//
     
    12161216        addl    %d1,%d0                 //subtract src from dest
    12171217        bgt     fix_stk
    1218        
    1219 //
    1220 // This code handles the case of the instruction resulting in 
     1218
     1219//
     1220// This code handles the case of the instruction resulting in
    12211221// an underflow condition.
    12221222//
     
    12481248frcunf_rnd:
    12491249        bsrl    unf_sub                 //get correct result based on
    1250 //                                      ;round precision/mode.  This 
     1250//                                      ;round precision/mode.  This
    12511251//                                      ;sets FPSR_CC correctly
    12521252        bfclr   WBTEMP_SGN(%a6){#0:#8}  //convert back to IEEE ext format
     
    12801280        sne     WBTEMP_SGN(%a6)
    12811281        bsrl    ovf_res                 //get correct result based on
    1282 //                                      ;round precision/mode.  This 
     1282//                                      ;round precision/mode.  This
    12831283//                                      ;sets FPSR_CC correctly
    12841284        bfclr   WBTEMP_SGN(%a6){#0:#8}  //convert back to IEEE ext format
     
    12871287frcfpn_clr:
    12881288        orl     #ovfinx_mask,USER_FPSR(%a6)
    1289 // 
     1289//
    12901290// Perform the write.
    12911291//
     
    13041304        beqs    frc0_dst
    13051305        cmpib   #1,%d0
    1306         beqs    frc1_dst 
     1306        beqs    frc1_dst
    13071307        cmpib   #2,%d0
    1308         beqs    frc2_dst 
     1308        beqs    frc2_dst
    13091309frc3_dst:
    13101310        movel   WBTEMP_EX(%a6),USER_FP3(%a6)
     
    13401340        btstb   #snan_bit,FPCR_ENABLE(%a6) //and don't overwrite
    13411341        beqs    fmoveinc                //the dest
    1342         movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for 
     1342        movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for
    13431343//                                              ;snan handler
    13441344        tstb    ETEMP(%a6)              //check for negative
     
    13641364        bnes    fminc_czero
    13651365        orl     #nan_mask,USER_FPSR(%a6) //if nan, nothing yet has set NaN
    1366         movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for 
     1366        movel   ETEMP_EX(%a6),FPTEMP_EX(%a6)    //set up fptemp sign for
    13671367//                                              ;snan handler
    13681368        tstw    LOCAL_EX(%a0)           //check sign
     
    13921392        beqs    fp0_dst
    13931393        cmpib   #1,%d0
    1394         beqs    fp1_dst 
     1394        beqs    fp1_dst
    13951395        cmpib   #2,%d0
    1396         beqs    fp2_dst 
     1396        beqs    fp2_dst
    13971397fp3_dst:
    13981398        movel   ETEMP_EX(%a6),USER_FP3(%a6)
     
    14241424        bra     mv_out
    14251425
    1426        
     1426
    14271427//
    14281428//      MOVE OUT
     
    14451445
    14461446//
    1447 // This exit is for move-out to memory.  The aunfl bit is 
     1447// This exit is for move-out to memory.  The aunfl bit is
    14481448// set if the result is inex and unfl is signalled.
    14491449//
     
    14691469        rts
    14701470//
    1471 // This exit is for move-out to int register.  The aunfl bit is 
     1471// This exit is for move-out to int register.  The aunfl bit is
    14721472// not set in any case for this move.
    14731473//
     
    14991499        fcmpd   #0x41dfffffffc00000,%fp0
    15001500// 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec
    1501         fbge    lo_plrg 
     1501        fbge    lo_plrg
    15021502        fcmpd   #0xc1e0000000000000,%fp0
    15031503// c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec
     
    15441544        fcmps   #0x46fffe00,%fp0
    15451545// 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec
    1546         fbge    wo_plrg 
     1546        fbge    wo_plrg
    15471547        fcmps   #0xc7000000,%fp0
    15481548// c7000000 in sgl prec = c00e00008000000000000000 in ext prec
     
    15891589        fcmps   #0x42fe0000,%fp0
    15901590// 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec
    1591         fbge    by_plrg 
     1591        fbge    by_plrg
    15921592        fcmps   #0xc3000000,%fp0
    15931593// c3000000 in sgl prec = c00600008000000000000000 in ext prec
     
    16321632        movel   #0,L_SCR1(%a6)  // initialize result to 0
    16331633        bfextu  FPCR_MODE(%a6){#2:#2},%d1       // d1 is the rounding mode
    1634         cmpb    #2,%d1         
     1634        cmpb    #2,%d1
    16351635        bmis    int_inx         // if RN or RZ, done
    16361636        bnes    int_rp          // if RP, continue below
     
    16451645        lea     L_SCR1(%a6),%a1 // a1 is address of L_SCR1
    16461646        addal   %d0,%a1         // offset by destination width -1
    1647         subal   #1,%a1         
     1647        subal   #1,%a1
    16481648        bsetb   #0,(%a1)                // set low bit at a1 address
    16491649int_inx:
     
    16591659        oril    #opaop_mask,USER_FPSR(%a6)
    16601660//                              ;fall through to perform int_wrt
    1661 int_wrt: 
     1661int_wrt:
    16621662        movel   EXC_EA(%a6),%a1 //load destination address
    16631663        tstl    %a1             //check to see if it is a dest register
    1664         beqs    wrt_dn          //write data register 
     1664        beqs    wrt_dn          //write data register
    16651665        lea     L_SCR1(%a6),%a0 //point to supervisor source address
    16661666        bsrl    mem_write
     
    16831683        movel   %d0,%d1         //reg_dest expects size:reg in d1
    16841684        bsrl    reg_dest        //load proper data register
    1685         bra     mvouti_end 
     1685        bra     mvouti_end
    16861686xp:
    16871687        lea     ETEMP(%a6),%a0
     
    17211721        cmpw    2(%a1),%d0
    17221722        bgt     dp_over
    1723        
     1723
    17241724        movel   #2,%d0          //set destination format to double
    17251725//                              ;fall through to do_fp
     
    17291729        swap    %d0                     //rnd prec in upper word
    17301730        addl    %d0,%d1                 //d1 has PREC/MODE info
    1731        
    1732         clrl    %d0                     //clear g,r,s 
    1733 
    1734         bsrl    round                   //round 
     1731
     1732        clrl    %d0                     //clear g,r,s
     1733
     1734        bsrl    round                   //round
    17351735
    17361736        movel   %a0,%a1
     
    17671767        bsetb   #unfl_bit,FPSR_EXCEPT(%a6)
    17681768        bra     mvout_end
    1769        
     1769
    17701770sp_under:
    17711771        bsetb   #etemp15_bit,STAG(%a6)
    17721772
    17731773        cmpw    4(%a1),%d0
    1774         blts    sp_catas        //catastrophic underflow case   
     1774        blts    sp_catas        //catastrophic underflow case
    17751775
    17761776        movel   #1,%d0          //load in round precision
     
    17871787        cmpw    4(%a1),%d0
    17881788        blts    dp_catas        //catastrophic underflow case
    1789                
     1789
    17901790        movel   #dbl_thresh,%d1 //load in double precision threshold
    1791         movel   #2,%d0         
     1791        movel   #2,%d0
    17921792        bsrl    dpspdnrm        //expects d1 to have proper
    17931793//                              ;denorm threshold
     
    18161816        movel   %a0,%a1         //a1 has the operand input
    18171817        movel   EXC_EA(%a6),%a0 //a0 has the destination pointer
    1818        
     1818
    18191819        bsrl    dest_sgl        //store the result
    18201820        oril    #unfinx_mask,USER_FPSR(%a6)
    18211821        bra     mvout_end
    1822        
     1822
    18231823dp_catas:
    18241824// Temp fix for z bit set in unf_sub
     
    18311831
    18321832        movel   #1,%d0
    1833         subw    %d0,LOCAL_EX(%a0) //account for difference between 
     1833        subw    %d0,LOCAL_EX(%a0) //account for difference between
    18341834//                              ;denorm/norm bias
    18351835
    18361836        movel   %a0,%a1         //a1 has the operand input
    18371837        movel   EXC_EA(%a6),%a0 //a0 has the destination pointer
    1838        
     1838
    18391839        bsrl    dest_dbl        //store the result
    18401840        oril    #unfinx_mask,USER_FPSR(%a6)
     
    19081908        bfextu  FPCR_MODE(%a6){#2:#2},%d1 //get rounding mode
    19091909        swap    %d1
    1910         movew   2(%a7),%d1      //set rounding precision 
     1910        movew   2(%a7),%d1      //set rounding precision
    19111911        swap    %d1             //at this point d1 has PREC/MODE info
    19121912        bsrl    round           //round result, sets the inex bit in
     
    19681968
    19691969//
    1970 // Also note that the dtag must be set to norm here - this is because 
     1970// Also note that the dtag must be set to norm here - this is because
    19711971// the 040 uses the dtag to execute the correct microcode.
    19721972//
  • c/src/lib/libcpu/m68k/m68040/fpsp/round.S

    r06731d6 r42e243e  
    1111//                      All Rights Reserved
    1212//
    13 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    14 //      The copyright notice above does not evidence any 
     13//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     14//      The copyright notice above does not evidence any
    1515//      actual or intended publication of such source code.
    1616
     
    2424//      round --- round result according to precision/mode
    2525//
    26 //      a0 points to the input operand in the internal extended format 
     26//      a0 points to the input operand in the internal extended format
    2727//      d1(high word) contains rounding precision:
    2828//              ext = $0000xxxx
     
    4747        .global round
    4848round:
    49 // If g=r=s=0 then result is exact and round is done, else set 
    50 // the inex flag in status reg and continue. 
    51 //
    52         bsrs    ext_grs                 //this subroutine looks at the 
    53 //                                      :rounding precision and sets 
     49// If g=r=s=0 then result is exact and round is done, else set
     50// the inex flag in status reg and continue.
     51//
     52        bsrs    ext_grs                 //this subroutine looks at the
     53//                                      :rounding precision and sets
    5454//                                      ;the appropriate g-r-s bits.
    5555        tstl    %d0                     //if grs are zero, go force
    5656        bne     rnd_cont                //lower bits to zero for size
    57        
     57
    5858        swap    %d1                     //set up d1.w for round prec.
    5959        bra     truncate
     
    9696rnd_mnus:
    9797        swap    %d1                     //set up d1 for round prec.
    98         tstb    LOCAL_SGN(%a0)          //check for sign       
     98        tstb    LOCAL_SGN(%a0)          //check for sign
    9999        bpl     truncate                //if negative then truncate
    100100        movel   #0xffffffff,%d0         //force g,r,s to be all f's
     
    132132// The ext_grs extract the guard/round/sticky bits according to the
    133133// selected rounding precision. It is called by the round subroutine
    134 // only.  All registers except d0 are kept intact. d0 becomes an 
     134// only.  All registers except d0 are kept intact. d0 becomes an
    135135// updated guard,round,sticky in d0{31:29}
    136136//
     
    143143        bnes    sgl_or_dbl
    144144        bras    end_ext_grs
    145  
     145
    146146sgl_or_dbl:
    147147        moveml  %d2/%d3,-(%a7)          //make some temp registers
     
    153153        lsll    %d2,%d3                 //shift g-r bits to MSB of d3
    154154        movel   LOCAL_HI(%a0),%d2               //get word 2 for s-bit test
    155         andil   #0x0000003f,%d2         //s bit is the or of all other 
     155        andil   #0x0000003f,%d2         //s bit is the or of all other
    156156        bnes    st_stky                 //bits to the right of g-r
    157157        tstl    LOCAL_LO(%a0)           //test lower mantissa
     
    160160        bnes    st_stky                 //if any are set, set sticky
    161161        bras    end_sd                  //if words 3 and 4 are clr, exit
    162 grs_dbl:   
     162grs_dbl:
    163163        bfextu  LOCAL_LO(%a0){#21:#2},%d3       //dbl-prec. g-r are 2 bits right
    164164        movel   #30,%d2                 //of the dbl prec. limits
    165165        lsll    %d2,%d3                 //shift g-r bits to the MSB of d3
    166166        movel   LOCAL_LO(%a0),%d2               //get lower mantissa  for s-bit test
    167         andil   #0x000001ff,%d2         //s bit is the or-ing of all 
     167        andil   #0x000001ff,%d2         //s bit is the or-ing of all
    168168        bnes    st_stky                 //other bits to the right of g-r
    169169        tstl    %d0                     //test word original g,r,s
     
    272272//      NORMALIZE
    273273//
    274 // These routines (nrm_zero & nrm_set) normalize the unnorm.  This 
    275 // is done by shifting the mantissa left while decrementing the 
     274// These routines (nrm_zero & nrm_set) normalize the unnorm.  This
     275// is done by shifting the mantissa left while decrementing the
    276276// exponent.
    277277//
    278 // NRM_SET shifts and decrements until there is a 1 set in the integer 
     278// NRM_SET shifts and decrements until there is a 1 set in the integer
    279279// bit of the mantissa (msb in d1).
    280280//
    281 // NRM_ZERO shifts and decrements until there is a 1 set in the integer 
    282 // bit of the mantissa (msb in d1) unless this would mean the exponent 
    283 // would go less than 0.  In that case the number becomes a denorm - the 
    284 // exponent (d0) is set to 0 and the mantissa (d1 & d2) is not 
     281// NRM_ZERO shifts and decrements until there is a 1 set in the integer
     282// bit of the mantissa (msb in d1) unless this would mean the exponent
     283// would go less than 0.  In that case the number becomes a denorm - the
     284// exponent (d0) is set to 0 and the mantissa (d1 & d2) is not
    285285// normalized.
    286286//
    287 // Note that both routines have been optimized (for the worst case) and 
     287// Note that both routines have been optimized (for the worst case) and
    288288// therefore do not have the easy to follow decrement/shift loop.
    289289//
     
    307307nrm_zero:
    308308        movew   LOCAL_EX(%a0),%d0
    309         cmpw   #64,%d0          //see if exp > 64 
     309        cmpw   #64,%d0          //see if exp > 64
    310310        bmis    d0_less
    311         bsr     nrm_set         //exp > 64 so exp won't exceed 0 
     311        bsr     nrm_set         //exp > 64 so exp won't exceed 0
    312312        rts
    313313d0_less:
     
    316316        movel   LOCAL_LO(%a0),%d2
    317317
    318         bfffo   %d1{#0:#32},%d3 //get the distance to the first 1 
     318        bfffo   %d1{#0:#32},%d3 //get the distance to the first 1
    319319//                              ;in ms mant
    320320        beqs    ms_clr          //branch if no bits were set
    321321        cmpw    %d3,%d0         //of X>Y
    322         bmis    greater         //then exp will go past 0 (neg) if 
     322        bmis    greater         //then exp will go past 0 (neg) if
    323323//                              ;it is just shifted
    324324        bsr     nrm_set         //else exp won't go past 0
    325325        moveml  (%a7)+,%d2/%d3/%d5/%d6
    326         rts     
     326        rts
    327327greater:
    328328        movel   %d2,%d6         //save ls mant in d6
     
    330330        lsll    %d0,%d1         //shift ms mant by count
    331331        movel   #32,%d5
    332         subl    %d0,%d5         //make op a denorm by shifting bits 
    333         lsrl    %d5,%d6         //by the number in the exp, then 
     332        subl    %d0,%d5         //make op a denorm by shifting bits
     333        lsrl    %d5,%d6         //by the number in the exp, then
    334334//                              ;set exp = 0.
    335335        orl     %d6,%d1         //shift the ls mant bits into the ms mant
    336         movel   #0,%d0          //same as if decremented exp to 0 
     336        movel   #0,%d0          //same as if decremented exp to 0
    337337//                              ;while shifting
    338338        movew   %d0,LOCAL_EX(%a0)
     
    383383
    384384//
    385 // We get here if ms mant was = 0, and we assume ls mant has bits 
     385// We get here if ms mant was = 0, and we assume ls mant has bits
    386386// set (otherwise this would have been tagged a zero not a denorm).
    387387//
     
    403403//      Used by underflow.
    404404//
    405 // Input: 
     405// Input:
    406406//      a0       points to the operand to be denormalized
    407407//               (in the internal extended format)
    408 //               
     408//
    409409//      d0:      rounding precision
    410410// Output:
     
    414414//      d0      is guard,round,sticky
    415415//
    416 // d0 comes into this routine with the rounding precision. It 
    417 // is then loaded with the denormalized exponent threshold for the 
     416// d0 comes into this routine with the rounding precision. It
     417// is then loaded with the denormalized exponent threshold for the
    418418// rounding precision.
    419419//
     
    422422denorm:
    423423        btstb   #6,LOCAL_EX(%a0)        //check for exponents between $7fff-$4000
    424         beqs    no_sgn_ext     
     424        beqs    no_sgn_ext
    425425        bsetb   #7,LOCAL_EX(%a0)        //sign extend if it is so
    426426no_sgn_ext:
     
    445445        subw    LOCAL_EX(%a0),%d0       //diff = threshold - exp
    446446        cmpw    #67,%d0         //if diff > 67 (mant + grs bits)
    447         bpls    chk_stky        //then branch (all bits would be 
     447        bpls    chk_stky        //then branch (all bits would be
    448448//                              ; shifted off in denorm routine)
    449449        clrl    %d0             //else clear the sticky flag
     
    458458        subw    LOCAL_EX(%a0),%d0       //diff = threshold - exp
    459459        cmpw    #67,%d0         //if diff > 67 (mant + grs bits)
    460         bpls    chk_stky        //then branch (all bits would be 
     460        bpls    chk_stky        //then branch (all bits would be
    461461//                              ; shifted off in denorm routine)
    462462        clrl    %d0             //else clear the sticky flag
     
    499499// The LOCAL_LO and LOCAL_GRS parts of the value are copied to FP_SCR2
    500500// so that bfext can be used to extract the new low part of the mantissa.
    501 // Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there 
     501// Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there
    502502// is no LOCAL_GRS scratch word following it on the fsave frame.
    503503//
     
    518518        subw    LOCAL_EX(%a0),%d1               //d1 = threshold - uns exponent
    519519        bles    no_lp                   //d1 <= 0
    520         cmpw    #32,%d1                 
    521         blts    case_1                  //0 = d1 < 32 
     520        cmpw    #32,%d1
     521        blts    case_1                  //0 = d1 < 32
    522522        cmpw    #64,%d1
    523523        blts    case_2                  //32 <= d1 < 64
     
    545545        movel   %d1,LOCAL_LO(%a0)               //store new LOCAL_LO
    546546        clrb    %d1
    547         bftst   %d0{#2:#30}     
     547        bftst   %d0{#2:#30}
    548548        beqs    c1nstky
    549549        bsetl   #rnd_stky_bit,%d0
     
    588588        andil   #0xe0000000,%d2         //clear all but G,R,S
    589589        tstl    %d2                     //test if original G,R,S are clear
    590         beqs    clear_grs               
     590        beqs    clear_grs
    591591        orl     #0x20000000,%d0         //set sticky bit in d0
    592592clear_grs:
     
    624624        andil   #0xc0000000,%d0
    625625        bras    c3com
    626        
     626
    627627sixty_five:
    628628        movel   LOCAL_HI(%a0),%d0
  • c/src/lib/libcpu/m68k/m68040/fpsp/rtems_skel.S

    r06731d6 r42e243e  
    2121//
    2222//      If the exception was completely handled by the package, then
    23 //      the return will be via a 'jmp fpsp_done'.  Unless there is 
     23//      the return will be via a 'jmp fpsp_done'.  Unless there is
    2424//      OS specific work to be done (such as handling a context switch or
    2525//      interrupt) the user program can be resumed via 'rte'.
     
    2828//      code is shown.  This code may need to be moved to an appropriate
    2929//      place in the target system, or rewritten.
    30 //     
     30//
    3131
    3232//              Copyright (C) Motorola, Inc. 1990
    3333//                      All Rights Reserved
    3434//
    35 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    36 //      The copyright notice above does not evidence any 
     35//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     36//      The copyright notice above does not evidence any
    3737//      actual or intended publication of such source code.
    3838
     
    6969//      All inexact exceptions are real, but the 'real' handler
    7070//      will probably want to clear the pending exception.
    71 //      The provided code will clear the E3 exception (if pending), 
     71//      The provided code will clear the E3 exception (if pending),
    7272//      otherwise clear the E1 exception.  The frestore is not really
    7373//      necessary for E1 exceptions.
     
    8383// that this fix is only for d43b parts, and is skipped if the
    8484// version number is not $40.
    85 // 
     85//
    8686//
    8787        .global SYM(_fpspEntry_inex)
     
    103103inex_ckofl:
    104104        btstb           #ovfl_bit,2(sp) //test for ovfl
    105         beq             inex_ckufl 
     105        beq             inex_ckufl
    106106        addl            #4,sp
    107107        frestore        (sp)+
     
    147147        unlk            a6
    148148        jmp     ([SYM(M68040FPSPUserExceptionHandlers)+2*4],%za0)
    149        
     149
    150150//
    151151//      Overflow exception
     
    165165        unlk            a6
    166166        jmp     ([SYM(M68040FPSPUserExceptionHandlers)+6*4],%za0)
    167        
     167
    168168//
    169169//      Underflow exception
     
    183183        unlk            a6
    184184        jmp     ([SYM(M68040FPSPUserExceptionHandlers)+4*4],%za0)
    185        
     185
    186186//
    187187//      Signalling NAN exception
     
    214214        unlk            a6
    215215        jmp     ([SYM(M68040FPSPUserExceptionHandlers)+5*4],%za0)
    216        
     216
    217217//
    218218//      BSUN exception
     
    238238//      F-line exception
    239239//
    240 //      A 'real' F-line exception is one that the FPSP is not supposed to 
     240//      A 'real' F-line exception is one that the FPSP is not supposed to
    241241//      handle. E.g. an instruction with a co-processor ID that is not 1.
    242242//
     
    342342//      d0 - number of bytes to read (maximum count is 12)
    343343//
    344 // Like mem_write, mem_read always reads with a supervisor 
     344// Like mem_write, mem_read always reads with a supervisor
    345345// destination address on the supervisor stack.  Also like mem_write,
    346346// the EXC_SR is checked and a simple memory copy is done if reading
  • c/src/lib/libcpu/m68k/m68040/fpsp/sacos.S

    r06731d6 r42e243e  
    1515//      Accuracy and Monotonicity: The returned result is within 3 ulps in
    1616//              64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
    17 //              result is subsequently rounded to double precision. The 
     17//              result is subsequently rounded to double precision. The
    1818//              result is provably monotonic in double precision.
    1919//
     
    4141//                      All Rights Reserved
    4242//
    43 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    44 //      The copyright notice above does not evidence any 
     43//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     44//      The copyright notice above does not evidence any
    4545//      actual or intended publication of such source code.
    4646
     
    113113        fmovel          %d1,%FPCR
    114114        fmoves          #0x00000000,%fp0
    115         rts                             //Facos ; of +1 is exact       
     115        rts                             //Facos ; of +1 is exact
    116116
    117117        |end
  • c/src/lib/libcpu/m68k/m68040/fpsp/sasin.S

    r06731d6 r42e243e  
    1515//      Accuracy and Monotonicity: The returned result is within 3 ulps in
    1616//              64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
    17 //              result is subsequently rounded to double precision. The 
     17//              result is subsequently rounded to double precision. The
    1818//              result is provably monotonic in double precision.
    1919//
     
    4141//                      All Rights Reserved
    4242//
    43 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    44 //      The copyright notice above does not evidence any 
     43//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     44//      The copyright notice above does not evidence any
    4545//      actual or intended publication of such source code.
    4646
     
    100100        oril            #0x3F800000,%d0 // ...+-1 IN SGL FORMAT
    101101        movel           %d0,-(%sp)      // ...push SIGN(X) IN SGL-FMT
    102         fmovel          %d1,%FPCR               
     102        fmovel          %d1,%FPCR
    103103        fmuls           (%sp)+,%fp0
    104104        bra             t_frcinx
  • c/src/lib/libcpu/m68k/m68040/fpsp/satan.S

    r06731d6 r42e243e  
    4646//                      All Rights Reserved
    4747//
    48 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    49 //      The copyright notice above does not evidence any 
     48//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     49//      The copyright notice above does not evidence any
    5050//      actual or intended publication of such source code.
    5151
     
    5555
    5656#include "fpsp.defs"
    57        
     57
    5858BOUNDS1:        .long 0x3FFB8000,0x4002FFFF
    5959
     
    325325//--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED
    326326
    327        
     327
    328328        fmovex          %fp0,%fp1
    329329        fmulx           %fp1,%fp1
     
    335335        fmuld           ATANA1,%fp1     // ...A1*U*V
    336336        fmulx           %fp2,%fp1               // ...A1*U*V*(A2+V*(A3+V))
    337        
     337
    338338        faddx           %fp1,%fp0               // ...ATAN(U), FP1 RELEASED
    339339        fmovel          %d1,%FPCR               //restore users exceptions
     
    359359        fmulx           %fp0,%fp0       // ...FP0 IS Y = X*X
    360360
    361        
     361
    362362        movew           #0x0000,XDCARE(%a6)
    363363
     
    384384
    385385        faddx           %fp2,%fp1               // ...[B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]
    386        
     386
    387387
    388388        fmulx           %fp1,%fp0       // ...X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))])
     
    416416        fdivx           %fp0,%fp1               // ...FP1 IS -1/X
    417417
    418        
     418
    419419//--DIVIDE IS STILL CRANKING
    420420
     
    442442
    443443        faddx           %fp2,%fp1               // ...[Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)]
    444        
     444
    445445
    446446        fmulx           %fp1,%fp0               // ...X'*Y*([B1+Z*(B3+Z*B5)]
     
    449449
    450450        fmovel          %d1,%FPCR               //restore users exceptions
    451        
     451
    452452        btstb           #7,(%a0)
    453453        beqs            pos_big
     
    477477        fsubx           PTINY,%fp0
    478478        bra             t_frcinx
    479        
     479
    480480        |end
  • c/src/lib/libcpu/m68k/m68040/fpsp/satanh.S

    r06731d6 r42e243e  
    1616//      Accuracy and Monotonicity: The returned result is within 3 ulps in
    1717//              64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
    18 //              result is subsequently rounded to double precision. The 
     18//              result is subsequently rounded to double precision. The
    1919//              result is provably monotonic in double precision.
    2020//
     
    3636//
    3737//      4. (|X| = 1) Generate infinity with an appropriate sign and
    38 //              divide-by-zero by       
     38//              divide-by-zero by
    3939//              sgn := sign(X)
    4040//              atan(X) := sgn / (+0).
     
    4848//                      All Rights Reserved
    4949//
    50 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    51 //      The copyright notice above does not evidence any 
     50//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     51//      The copyright notice above does not evidence any
    5252//      actual or intended publication of such source code.
    5353
  • c/src/lib/libcpu/m68k/m68040/fpsp/scale.S

    r06731d6 r42e243e  
    1212//      the fscale unimplemented instruction.
    1313//
    14 //      Input: Double-extended destination operand in FPTEMP, 
     14//      Input: Double-extended destination operand in FPTEMP,
    1515//              double-extended source operand in ETEMP.
    1616//
     
    2020//
    2121//      Algorithm:
    22 //             
     22//
    2323//              Copyright (C) Motorola, Inc. 1990
    2424//                      All Rights Reserved
    2525//
    26 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    27 //      The copyright notice above does not evidence any 
     26//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     27//      The copyright notice above does not evidence any
    2828//      actual or intended publication of such source code.
    2929
     
    150150        addl            %d0,%d1         //add src to dest
    151151        beqs            denorm          //if zero, result is denorm
    152         blts            fix_dnrm        //if negative, result is 
     152        blts            fix_dnrm        //if negative, result is
    153153//                                      ;needing denormalization
    154154        tstb            L_SCR1(%a6)
     
    164164//
    165165// The result exponent is below denorm value.  Test for catastrophic
    166 // underflow and force zero if true.  If not, try to shift the 
     166// underflow and force zero if true.  If not, try to shift the
    167167// mantissa right until a zero exponent exists.
    168168//
     
    232232
    233233//
    234 // The rounding mode changed the zero to a smallest denorm. Call 
     234// The rounding mode changed the zero to a smallest denorm. Call
    235235// t_resdnrm with exceptional operand in ETEMP.
    236236//
     
    253253        bras            sm_dnrm
    254254
    255        
     255
    256256//
    257257// The result has underflowed to zero. Return zero and set
     
    287287        clrl            FP_SCR1+4(%a6)  //for gen_except.
    288288        clrl            FP_SCR1+8(%a6)
    289         fmoves          #0x80000000,%fp0       
     289        fmoves          #0x80000000,%fp0
    290290        rts
    291291pos_zero:
     
    302302//
    303303dst_dnrm:
    304         moveml          %d2/%d3,-(%a7) 
     304        moveml          %d2/%d3,-(%a7)
    305305        movew           FPTEMP_EX(%a6),%d1
    306306        movel           FPTEMP_HI(%a6),%d2
     
    316316        bras            dst_loop
    317317//
    318 // Destination became normalized.  Simply add the remaining 
     318// Destination became normalized.  Simply add the remaining
    319319// portion of the src to the exponent.
    320320//
  • c/src/lib/libcpu/m68k/m68040/fpsp/scosh.S

    r06731d6 r42e243e  
    5252//                      All Rights Reserved
    5353//
    54 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    55 //      The copyright notice above does not evidence any 
     54//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     55//      The copyright notice above does not evidence any
    5656//      actual or intended publication of such source code.
    5757
  • c/src/lib/libcpu/m68k/m68040/fpsp/setox.S

    r06731d6 r42e243e  
    334334//                      All Rights Reserved
    335335//
    336 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    337 //      The copyright notice above does not evidence any 
     336//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     337//      The copyright notice above does not evidence any
    338338//      actual or intended publication of such source code.
    339339
  • c/src/lib/libcpu/m68k/m68040/fpsp/sgetem.S

    r06731d6 r42e243e  
    44//      sgetem.sa 3.1 12/10/90
    55//
    6 //      The entry point sGETEXP returns the exponent portion 
     6//      The entry point sGETEXP returns the exponent portion
    77//      of the input argument.  The exponent bias is removed
    8 //      and the exponent value is returned as an extended 
     8//      and the exponent value is returned as an extended
    99//      precision number in fp0.  sGETEXPD handles denormalized
    1010//      numbers.
    1111//
    12 //      The entry point sGETMAN extracts the mantissa of the 
    13 //      input argument.  The mantissa is converted to an 
     12//      The entry point sGETMAN extracts the mantissa of the
     13//      input argument.  The mantissa is converted to an
    1414//      extended precision number and returned in fp0.  The
    1515//      range of the result is [1.0 - 2.0).
     
    2727//                      All Rights Reserved
    2828//
    29 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    30 //      The copyright notice above does not evidence any 
     29//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     30//      The copyright notice above does not evidence any
    3131//      actual or intended publication of such source code.
    3232
  • c/src/lib/libcpu/m68k/m68040/fpsp/sint.S

    r06731d6 r42e243e  
    44//      sint.sa 3.1 12/10/90
    55//
    6 //      The entry point sINT computes the rounded integer 
    7 //      equivalent of the input argument, sINTRZ computes 
     6//      The entry point sINT computes the rounded integer
     7//      equivalent of the input argument, sINTRZ computes
    88//      the integer rounded to zero of the input argument.
    99//
     
    2727//      Algorithm: (sint and sintrz)
    2828//
    29 //      1. If exp(X) >= 63, return X. 
     29//      1. If exp(X) >= 63, return X.
    3030//         If exp(X) < 0, return +/- 0 or +/- 1, according to
    3131//         the rounding mode.
    32 //     
     32//
    3333//      2. (X is in range) set rsc = 63 - exp(X). Unnormalize the
    3434//         result to the exponent $403e.
     
    5454//                      All Rights Reserved
    5555//
    56 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    57 //      The copyright notice above does not evidence any 
     56//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     57//      The copyright notice above does not evidence any
    5858//      actual or intended publication of such source code.
    5959
     
    8181        bfextu  FPCR_MODE(%a6){#2:#2},%d1       //use user's mode for rounding
    8282//                                      ;implicitly has extend precision
    83 //                                      ;in upper word. 
     83//                                      ;in upper word.
    8484        movel   %d1,L_SCR1(%a6)         //save mode bits
    85         bras    sintexc                 
     85        bras    sintexc
    8686
    8787//
     
    118118        movel   #1,L_SCR1(%a6)          //use rz mode for rounding
    119119//                                      ;implicitly has extend precision
    120 //                                      ;in upper word. 
    121         bras    sintexc                 
     120//                                      ;in upper word.
     121        bras    sintexc
    122122//
    123123//      SINTDO
    124124//
    125125//      Input:  a0 points to an IEEE extended format operand
    126 //      Output: fp0 has the result 
     126//      Output: fp0 has the result
    127127//
    128128// Exceptions:
     
    136136        bfextu  FPCR_MODE(%a6){#2:#2},%d1       //use user's mode for rounding
    137137//                                      ;implicitly has ext precision
    138 //                                      ;in upper word. 
     138//                                      ;in upper word.
    139139        movel   %d1,L_SCR1(%a6)         //save mode bits
    140140//
     
    144144        bclrb   #sign_bit,LOCAL_EX(%a0) //convert to internal extended
    145145//                                      ;format
    146         sne     LOCAL_SGN(%a0)         
     146        sne     LOCAL_SGN(%a0)
    147147        cmpw    #0x403e,LOCAL_EX(%a0)   //check if (unbiased) exp > 63
    148148        bgts    out_rnge                        //branch if exp < 63
     
    190190        bsr     ld_mzero
    191191        bra     t_inx2
    192        
     192
    193193//
    194194// Input is greater than 2^63.  All bits are significant.  Return
  • c/src/lib/libcpu/m68k/m68040/fpsp/slog2.S

    r06731d6 r42e243e  
    44//      slog2.sa 3.1 12/10/90
    55//
    6 //       The entry point slog10 computes the base-10 
     6//       The entry point slog10 computes the base-10
    77//      logarithm of an input argument X.
    8 //      slog10d does the same except the input value is a 
    9 //      denormalized number. 
     8//      slog10d does the same except the input value is a
     9//      denormalized number.
    1010//      sLog2 and sLog2d are the base-2 analogues.
    1111//
    12 //       INPUT: Double-extended value in memory location pointed to 
     12//       INPUT: Double-extended value in memory location pointed to
    1313//              by address register a0.
    1414//
    15 //       OUTPUT: log_10(X) or log_2(X) returned in floating-point 
     15//       OUTPUT: log_10(X) or log_2(X) returned in floating-point
    1616//              register fp0.
    1717//
    18 //       ACCURACY and MONOTONICITY: The returned result is within 1.7 
    19 //              ulps in 64 significant bit, i.e. within 0.5003 ulp 
    20 //              to 53 bits if the result is subsequently rounded 
    21 //              to double precision. The result is provably monotonic 
     18//       ACCURACY and MONOTONICITY: The returned result is within 1.7
     19//              ulps in 64 significant bit, i.e. within 0.5003 ulp
     20//              to 53 bits if the result is subsequently rounded
     21//              to double precision. The result is provably monotonic
    2222//              in double precision.
    2323//
    24 //       SPEED: Two timings are measured, both in the copy-back mode. 
    25 //              The first one is measured when the function is invoked 
    26 //              the first time (so the instructions and data are not 
    27 //              in cache), and the second one is measured when the 
     24//       SPEED: Two timings are measured, both in the copy-back mode.
     25//              The first one is measured when the function is invoked
     26//              the first time (so the instructions and data are not
     27//              in cache), and the second one is measured when the
    2828//              function is reinvoked at the same input argument.
    2929//
     
    4545//
    4646//
    47 //       slog10: 
     47//       slog10:
    4848//
    4949//       Step 0.   If X < 0, create a NaN and raise the invalid operation
     
    9999//                      All Rights Reserved
    100100//
    101 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    102 //      The copyright notice above does not evidence any 
     101//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     102//      The copyright notice above does not evidence any
    103103//      actual or intended publication of such source code.
    104104
     
    107107        |section        8
    108108
    109         |xref   t_frcinx       
     109        |xref   t_frcinx
    110110        |xref   t_operr
    111111        |xref   slogn
  • c/src/lib/libcpu/m68k/m68040/fpsp/slogn.S

    r06731d6 r42e243e  
    1616//      Accuracy and Monotonicity: The returned result is within 2 ulps in
    1717//              64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
    18 //              result is subsequently rounded to double precision. The 
     18//              result is subsequently rounded to double precision. The
    1919//              result is provably monotonic in double precision.
    2020//
    21 //      Speed: The program slogn takes approximately 190 cycles for input 
    22 //              argument X such that |X-1| >= 1/16, which is the the usual 
     21//      Speed: The program slogn takes approximately 190 cycles for input
     22//              argument X such that |X-1| >= 1/16, which is the the usual
    2323//              situation. For those arguments, slognp1 takes approximately
    2424//               210 cycles. For the less common arguments, the program will
     
    4848//              of the algorithm for LOGN and compute log(1+X) as
    4949//              k*log(2) + log(F) + poly where poly approximates log(1+u),
    50 //              u = (Y-F)/F. 
     50//              u = (Y-F)/F.
    5151//
    5252//      Implementation Notes:
    5353//      Note 1. There are 64 different possible values for F, thus 64 log(F)'s
    54 //              need to be tabulated. Moreover, the values of 1/F are also 
     54//              need to be tabulated. Moreover, the values of 1/F are also
    5555//              tabulated so that the division in (Y-F)/F can be performed by a
    5656//              multiplication.
    5757//
    5858//      Note 2. In Step 2 of lognp1, in order to preserved accuracy, the value
    59 //              Y-F has to be calculated carefully when 1/2 <= X < 3/2. 
     59//              Y-F has to be calculated carefully when 1/2 <= X < 3/2.
    6060//
    6161//      Note 3. To fully exploit the pipeline, polynomials are usually separated
    6262//              into two parts evaluated independently before being added up.
    63 //     
     63//
    6464
    6565//              Copyright (C) Motorola, Inc. 1990
    6666//                      All Rights Reserved
    6767//
    68 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    69 //      The copyright notice above does not evidence any 
     68//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     69//      The copyright notice above does not evidence any
    7070//      actual or intended publication of such source code.
    7171
     
    265265//----Note that this code assumes the denormalized input is NON-ZERO.
    266266
    267      moveml     %d2-%d7,-(%a7)          // ...save some registers 
     267     moveml     %d2-%d7,-(%a7)          // ...save some registers
    268268     movel      #0x00000000,%d3         // ...D3 is exponent of smallest norm. #
    269269     movel      4(%a0),%d4
     
    350350//--LOG(1+U) CAN BE VERY EFFICIENT.
    351351//--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO
    352 //--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. 
     352//--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
    353353
    354354//--GET K, Y, F, AND ADDRESS OF 1/F.
     
    366366        oril    #0x01000000,FFRAC(%a6) // ...GET F: ATTACH A 1 AT THE EIGHTH BIT
    367367        movel   FFRAC(%a6),%d0  // ...READY TO GET ADDRESS OF 1/F
    368         andil   #0x7E000000,%d0 
     368        andil   #0x7E000000,%d0
    369369        asrl    #8,%d0
    370370        asrl    #8,%d0
     
    393393
    394394        fmovex  %fp2,%fp3
    395         fmovex  %fp2,%fp1       
     395        fmovex  %fp2,%fp1
    396396
    397397        fmuld   LOGA6,%fp1      // ...V*A6
     
    443443        fmulx   %fp0,%fp0       // ...FP0 IS V
    444444        fmovex  %fp1,SAVEU(%a6) // ...STORE U IN MEMORY, FREE FP1
    445         fmovex  %fp0,%fp1       
     445        fmovex  %fp0,%fp1
    446446        fmulx   %fp1,%fp1       // ...FP1 IS W
    447447
     
    468468
    469469        fmovel  %d1,%fpcr
    470         faddx   SAVEU(%a6),%fp0         
     470        faddx   SAVEU(%a6),%fp0
    471471        bra     t_frcinx
    472472        rts
     
    552552        asrl    #4,%d0          // ...D0 CONTAINS DISPLACEMENT FOR 1/F
    553553        faddx   %fp1,%fp1               // ...GET 2Z
    554         fmovemx %fp2-%fp2/%fp3,-(%sp)   // ...SAVE FP2 
     554        fmovemx %fp2-%fp2/%fp3,-(%sp)   // ...SAVE FP2
    555555        faddx   %fp1,%fp0               // ...FP0 IS Y-F = (2-F)+2Z
    556556        lea     LOGTBL,%a0      // ...A0 IS ADDRESS OF 1/F
  • c/src/lib/libcpu/m68k/m68040/fpsp/smovecr.S

    r06731d6 r42e243e  
    1818//                      All Rights Reserved
    1919//
    20 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    21 //      The copyright notice above does not evidence any 
     20//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     21//      The copyright notice above does not evidence any
    2222//      actual or intended publication of such source code.
    2323
     
    4242FZERO:  .long   00000000
    4343//
    44 //      FMOVECR 
     44//      FMOVECR
    4545//
    4646        .global smovcr
     
    5858        bles    SM_TBL          //valid constants in this range
    5959        cmpib   #0x2f,%d0               //check range $10 - $2f
    60         bles    Z_VAL           //if in this range, return zero 
     60        bles    Z_VAL           //if in this range, return zero
    6161        cmpib   #0x3f,%d0               //check range $30 - $3f
    6262        ble     BG_TBL          //valid constants in this range
     
    152152        btstb   #sign_bit,LOCAL_EX(%a0)
    153153        sne     LOCAL_SGN(%a0)          //convert to internal ext. format
    154        
     154
    155155        bsr     round                   //go round the mantissa
    156156
  • c/src/lib/libcpu/m68k/m68040/fpsp/srem_mod.S

    r06731d6 r42e243e  
    2424//
    2525//       Step 1.  Save and strip signs of X and Y: signX := sign(X),
    26 //                signY := sign(Y), X := |X|, Y := |Y|, 
     26//                signY := sign(Y), X := |X|, Y := |Y|,
    2727//                signQ := signX EOR signY. Record whether MOD or REM
    2828//                is requested.
     
    4444//       Step 4.  At this point, R = X - QY = MOD(X,Y). Set
    4545//                Last_Subtract := false (used in Step 7 below). If
    46 //                MOD is requested, go to Step 6. 
     46//                MOD is requested, go to Step 6.
    4747//
    4848//       Step 5.  R = MOD(X,Y), but REM(X,Y) is requested.
     
    6464//                R := 0. Return signQ, last 7 bits of Q, and R.
    6565//
    66 //               
    67              
     66//
     67
    6868//              Copyright (C) Motorola, Inc. 1990
    6969//                      All Rights Reserved
    7070//
    71 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    72 //      The copyright notice above does not evidence any 
     71//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     72//      The copyright notice above does not evidence any
    7373//      actual or intended publication of such source code.
    7474
     
    365365//
    366366Get_Q:
    367    clrl         %d6             
     367   clrl         %d6
    368368   movew               SignQ(%a6),%d6        // ...D6 is sign(Q)
    369369   movel               #8,%d7
    370    lsrl                %d7,%d6           
     370   lsrl                %d7,%d6
    371371   andil               #0x0000007F,%d3   // ...7 bits of Q
    372372   orl                 %d6,%d3           // ...sign and bits of Q
     
    394394//..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1)
    395395   addql               #1,%d3
    396    cmpil               #8,%d0           // ...D0 is j 
     396   cmpil               #8,%d0           // ...D0 is j
    397397   bges                Q_Big
    398398
  • c/src/lib/libcpu/m68k/m68040/fpsp/ssin.S

    r06731d6 r42e243e  
    8686//                      All Rights Reserved
    8787//
    88 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    89 //      The copyright notice above does not evidence any 
     88//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     89//      The copyright notice above does not evidence any
    9090//      actual or intended publication of such source code.
    9191
     
    207207//--HIDE THE NEXT THREE INSTRUCTIONS
    208208        lea             PITBL+0x200,%a1 // ...TABLE OF N*PI/2, N = -32,...,32
    209        
     209
    210210
    211211//--FP1 IS NOW READY
     
    276276//--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING
    277277//--FP2 RELEASED, RESTORE NOW AND TAKE FULL ADVANTAGE OF HIDING
    278        
     278
    279279
    280280        fmulx           %fp1,%fp0               // ...SIN(R')-R'
     
    338338//--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING
    339339//--FP2 RELEASED.
    340        
     340
    341341
    342342        faddx           %fp1,%fp0
     
    355355        cmpil           #0x3FFF8000,%d0
    356356        bgts            REDUCEX
    357        
     357
    358358
    359359SINSM:
     
    469469        clrw           FP_SCR2+2(%a6)
    470470        movel           #0xC90FDAA2,FP_SCR2+4(%a6)
    471         clrl            FP_SCR2+8(%a6)          // ...FP_SCR2 is  2**(L) * Piby2_1     
     471        clrl            FP_SCR2+8(%a6)          // ...FP_SCR2 is  2**(L) * Piby2_1
    472472
    473473//--FP2 IS READY
     
    517517        fmovemx (%a7)+,%fp2-%fp5
    518518
    519        
     519
    520520        movel           ADJN(%a6),%d0
    521521        cmpil           #4,%d0
     
    562562//--HIDE THE NEXT THREE INSTRUCTIONS
    563563        lea             PITBL+0x200,%a1 // ...TABLE OF N*PI/2, N = -32,...,32
    564        
     564
    565565
    566566//--FP1 IS NOW READY
     
    580580        movel           N(%a6),%d0
    581581        rorl            #1,%d0
    582        
     582
    583583        cmpil           #0,%d0          // ...D0 < 0 IFF N IS ODD
    584584        bge             NEVEN
     
    644644        fmulx           %fp2,%fp0        // ...S(B2+...)
    645645
    646        
     646
    647647
    648648        fmulx           RPRIME(%a6),%fp1        // ...R'S(A1+...)
     
    712712        fmulx           %fp2,%fp0        // ...s(a1+...)
    713713
    714        
     714
    715715
    716716        fadds           COSB1,%fp1      // ...B1+S(B2...)
     
    731731        cmpil           #0x3FFF8000,%d0
    732732        bgt             REDUCEX
    733        
     733
    734734
    735735SCSM:
  • c/src/lib/libcpu/m68k/m68040/fpsp/ssinh.S

    r06731d6 r42e243e  
    88//       input.
    99//
    10 //       Input: Double-extended number X in location pointed to 
     10//       Input: Double-extended number X in location pointed to
    1111//              by address register a0.
    1212//
     
    5252//                      All Rights Reserved
    5353//
    54 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    55 //      The copyright notice above does not evidence any 
     54//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     55//      The copyright notice above does not evidence any
    5656//      actual or intended publication of such source code.
    5757
  • c/src/lib/libcpu/m68k/m68040/fpsp/stan.S

    r06731d6 r42e243e  
    5353//                      All Rights Reserved
    5454//
    55 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    56 //      The copyright notice above does not evidence any 
     55//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     56//      The copyright notice above does not evidence any
    5757//      actual or intended publication of such source code.
    5858
     
    240240
    241241        fmulx           %fp3,%fp1               // ...S(Q1+S(Q2+S(Q3+SQ4)))
    242        
     242
    243243
    244244        faddx           %fp2,%fp0               // ...R+RS(P1+S(P2+SP3))
    245        
     245
    246246
    247247        fadds           #0x3F800000,%fp1        // ...1+S(Q1+...)
     
    278278
    279279        fmulx           %fp3,%fp0               // ...S(Q1+S(Q2+S(Q3+SQ4)))
    280        
     280
    281281
    282282        faddx           %fp2,%fp1               // ...R+RS(P1+S(P2+SP3))
    283283        fadds           #0x3F800000,%fp0        // ...1+S(Q1+...)
    284        
     284
    285285
    286286        fmovex          %fp1,-(%sp)
     
    400400        clrw           FP_SCR2+2(%a6)
    401401        movel           #0xC90FDAA2,FP_SCR2+4(%a6)
    402         clrl            FP_SCR2+8(%a6)          // ...FP_SCR2 is  2**(L) * Piby2_1     
     402        clrl            FP_SCR2+8(%a6)          // ...FP_SCR2 is  2**(L) * Piby2_1
    403403
    404404//--FP2 IS READY
     
    448448        fmovemx (%a7)+,%fp2-%fp5
    449449
    450        
     450
    451451        movel           N(%a6),%d0
    452452        rorl            #1,%d0
  • c/src/lib/libcpu/m68k/m68040/fpsp/stanh.S

    r06731d6 r42e243e  
    5252//                      All Rights Reserved
    5353//
    54 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    55 //      The copyright notice above does not evidence any 
     54//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     55//      The copyright notice above does not evidence any
    5656//      actual or intended publication of such source code.
    5757
     
    5959
    6060        |section        8
    61        
     61
    6262#include "fpsp.defs"
    6363
  • c/src/lib/libcpu/m68k/m68040/fpsp/sto_res.S

    r06731d6 r42e243e  
    88//      users destination register then fp0 is moved to the the
    99//      correct floating-point destination register.  fp0 and fp1
    10 //      are then restored to the original contents. 
     10//      are then restored to the original contents.
    1111//
    12 //      Input:  result in fp0,fp1 
     12//      Input:  result in fp0,fp1
    1313//
    1414//              d2 & a0 should be kept unmodified
     
    2222//                      All Rights Reserved
    2323//
    24 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    25 //      The copyright notice above does not evidence any 
     24//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     25//      The copyright notice above does not evidence any
    2626//      actual or intended publication of such source code.
    2727
  • c/src/lib/libcpu/m68k/m68040/fpsp/stwotox.S

    r06731d6 r42e243e  
    7979//                      All Rights Reserved
    8080//
    81 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    82 //      The copyright notice above does not evidence any 
     81//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     82//      The copyright notice above does not evidence any
    8383//      actual or intended publication of such source code.
    8484
     
    225225        bles            TWOMAIN
    226226        bra             EXPBORS
    227        
     227
    228228
    229229TWOMAIN:
     
    232232        fmovex          %fp0,%fp1
    233233        fmuls           #0x42800000,%fp1  // ...64 * X
    234        
     234
    235235        fmovel          %fp1,N(%a6)             // ...N = ROUND-TO-INT(64 X)
    236236        movel           %d2,-(%sp)
     
    267267        clrl            FACT2LOW(%a6)
    268268        addw            %d0,FACT1(%a6)
    269        
     269
    270270        fmulx           LOG2,%fp0       // ...FP0 IS R
    271271        addw            %d0,FACT2(%a6)
     
    335335        fmovex          %fp0,%fp1
    336336        fmuld           L2TEN64,%fp1    // ...X*64*LOG10/LOG2
    337        
     337
    338338        fmovel          %fp1,N(%a6)             // ...N=INT(X*64*LOG10/LOG2)
    339339        movel           %d2,-(%sp)
     
    378378
    379379        fmulx           LOG10,%fp0      // ...FP0 IS R
    380        
     380
    381381        addw            %d0,FACT1(%a6)
    382382        addw            %d0,FACT2(%a6)
     
    408408        fmulx           %fp1,%fp2               // ...FP2 IS S*(A1+S*(A3+S*A5))
    409409        faddx           %fp3,%fp0               // ...FP0 IS R+R*S*(A2+S*A4)
    410        
     410
    411411        faddx           %fp2,%fp0               // ...FP0 IS EXP(R) - 1
    412        
     412
    413413
    414414//--FINAL RECONSTRUCTION PROCESS
  • c/src/lib/libcpu/m68k/m68040/fpsp/tbldo.S

    r06731d6 r42e243e  
    99//                      functions.  Dyadic functions require two
    1010//                      levels, and the tables are still contained
    11 //                      in do_func.  The table is arranged for 
     11//                      in do_func.  The table is arranged for
    1212//                      index with a 10-bit index, with the first
    1313//                      7 bits the opcode, and the remaining 3
    1414//                      the stag.  For dyadic functions, all
    1515//                      valid addresses are to the generic entry
    16 //                      point. 
     16//                      point.
    1717//
    1818
     
    2020//                      All Rights Reserved
    2121//
    22 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    23 //      The copyright notice above does not evidence any 
     22//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     23//      The copyright notice above does not evidence any
    2424//      actual or intended publication of such source code.
    2525
     
    6060
    6161        .long   sint            //$01-0 fint norm
    62         .long   szero           //$01-1 fint zero 
     62        .long   szero           //$01-1 fint zero
    6363        .long   sinf            //$01-2 fint inf
    6464        .long   src_nan         //$01-3 fint nan
  • c/src/lib/libcpu/m68k/m68040/fpsp/util.S

    r06731d6 r42e243e  
    77//
    88//      ovf_res: used by overflow to force the correct
    9 //               result. ovf_r_k, ovf_r_x2, ovf_r_x3 are 
     9//               result. ovf_r_k, ovf_r_x2, ovf_r_x3 are
    1010//               derivatives of this routine.
    1111//      get_fline: get user's opcode word
    1212//      g_dfmtou: returns the destination format.
    1313//      g_opcls: returns the opclass of the float instruction.
    14 //      g_rndpr: returns the rounding precision. 
     14//      g_rndpr: returns the rounding precision.
    1515//      reg_dest: write byte, word, or long data to Dn
    1616//
     
    1919//                      All Rights Reserved
    2020//
    21 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    22 //      The copyright notice above does not evidence any 
     21//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     22//      The copyright notice above does not evidence any
    2323//      actual or intended publication of such source code.
    2424
     
    4242// the exponent.
    4343//                                      ;+inf
    44 EXT_PINF:       .long   0x7fff0000,0x00000000,0x00000000,0x00000000     
     44EXT_PINF:       .long   0x7fff0000,0x00000000,0x00000000,0x00000000
    4545//                                      ;largest +ext
    46 EXT_PLRG:       .long   0x7ffe0000,0xffffffff,0xffffffff,0x00000000     
     46EXT_PLRG:       .long   0x7ffe0000,0xffffffff,0xffffffff,0x00000000
    4747//                                      ;largest magnitude +sgl in ext
    48 SGL_PLRG:       .long   0x407e0000,0xffffff00,0x00000000,0x00000000     
     48SGL_PLRG:       .long   0x407e0000,0xffffff00,0x00000000,0x00000000
    4949//                                      ;largest magnitude +dbl in ext
    50 DBL_PLRG:       .long   0x43fe0000,0xffffffff,0xfffff800,0x00000000     
     50DBL_PLRG:       .long   0x43fe0000,0xffffffff,0xfffff800,0x00000000
    5151//                                      ;largest -ext
    5252
     
    7373//      ovf_r_k --- overflow result calculation
    7474//
    75 // This entry point is used by kernel_ex. 
     75// This entry point is used by kernel_ex.
    7676//
    7777// This forces the destination precision to be extended
     
    8282        .global ovf_r_k
    8383ovf_r_k:
    84         lea     ETEMP(%a6),%a0  //a0 points to source operand   
     84        lea     ETEMP(%a6),%a0  //a0 points to source operand
    8585        bclrb   #sign_bit,ETEMP_EX(%a6)
    8686        sne     ETEMP_SGN(%a6)  //convert to internal IEEE format
     
    115115        movew   CMDREG3B(%a6),%d0               //get the command word again
    116116        andil   #0x7f,%d0                       //clear all except operation
    117         cmpil   #0x33,%d0                       
     117        cmpil   #0x33,%d0
    118118        beql    ovf_fsgl                //fsglmul or fsgldiv
    119119        cmpil   #0x30,%d0
    120         beql    ovf_fsgl               
     120        beql    ovf_fsgl
    121121        bra     ovf_fpcr                //instruction is none of the above
    122122//                                      ;use FPCR
     
    135135        beql    ovf_fsgl                //fsgldiv
    136136        bra     ovf_fpcr                //none of the above, use FPCR
    137 // 
     137//
    138138//
    139139// Inst is either fsgldiv or fsglmul.  Force extended precision.
     
    155155        bfextu  FPCR_MODE(%a6){#0:#2},%d0 //set round precision
    156156        bra     ovf_res
    157        
     157
    158158//
    159159//
     
    195195        leal    EXT_PINF,%a1    //answer is +/- infinity
    196196        bsetb   #inf_bit,FPSR_CC(%a6)
    197         bra     set_sign        //now go set the sign   
     197        bra     set_sign        //now go set the sign
    198198EXT_RZ:
    199199        leal    EXT_PLRG,%a1    //answer is +/- large number
     
    316316//
    317317//      g_rndpr --- put rounding precision in d0{1:0}
    318 //     
     318//
    319319//      valid return codes are:
    320 //              00 - extended 
     320//              00 - extended
    321321//              01 - single
    322322//              10 - double
     
    353353// is the same as the rounding precision.  Pass results from g_dfmtou.
    354354//
    355         bsr     g_dfmtou       
     355        bsr     g_dfmtou
    356356        rts
    357357op_0x0:
     
    367367        movew   CMDREG3B(%a6),%d0       //get the command word again
    368368        andil   #0x7f,%d0               //clear all except operation
    369         cmpil   #0x33,%d0                       
     369        cmpil   #0x33,%d0
    370370        beql    unf_fsgl        //fsglmul or fsgldiv
    371371        cmpil   #0x30,%d0
     
    411411//
    412412unf_fsgl:
    413         movel   #0,%d0         
     413        movel   #0,%d0
    414414        rts
    415415//
     
    439439//      If E3, the format is extended.
    440440//
    441 //      Dest. Fmt.     
     441//      Dest. Fmt.
    442442//              extended  010 -> 00
    443443//              single    001 -> 01
     
    471471// the exponent.
    472472//                                      ;+zero
    473 EXT_PZRO:       .long   0x00000000,0x00000000,0x00000000,0x00000000     
     473EXT_PZRO:       .long   0x00000000,0x00000000,0x00000000,0x00000000
    474474//                                      ;+zero
    475 SGL_PZRO:       .long   0x3f810000,0x00000000,0x00000000,0x00000000     
     475SGL_PZRO:       .long   0x3f810000,0x00000000,0x00000000,0x00000000
    476476//                                      ;+zero
    477 DBL_PZRO:       .long   0x3c010000,0x00000000,0x00000000,0x00000000     
     477DBL_PZRO:       .long   0x3c010000,0x00000000,0x00000000,0x00000000
    478478//                                      ;smallest +ext denorm
    479 EXT_PSML:       .long   0x00000000,0x00000000,0x00000001,0x00000000     
     479EXT_PSML:       .long   0x00000000,0x00000000,0x00000001,0x00000000
    480480//                                      ;smallest +sgl denorm
    481 SGL_PSML:       .long   0x3f810000,0x00000100,0x00000000,0x00000000     
     481SGL_PSML:       .long   0x3f810000,0x00000100,0x00000000,0x00000000
    482482//                                      ;smallest +dbl denorm
    483 DBL_PSML:       .long   0x3c010000,0x00000000,0x00000800,0x00000000     
     483DBL_PSML:       .long   0x3c010000,0x00000000,0x00000800,0x00000000
    484484//
    485485//      UNF_SUB --- underflow result calculation
     
    525525        leal    EXT_PZRO,%a1    //answer is +/- zero
    526526        bsetb   #z_bit,FPSR_CC(%a6)
    527         bra     uset_sign       //now go set the sign   
     527        bra     uset_sign       //now go set the sign
    528528uEXT_RZ:
    529529        leal    EXT_PZRO,%a1    //answer is +/- zero
     
    632632//
    633633// Input:
    634 //      L_SCR1: Data 
     634//      L_SCR1: Data
    635635//      d1:     data size and dest register number formatted as:
    636636//
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_bsun.S

    r06731d6 r42e243e  
    1616//                      All Rights Reserved
    1717//
    18 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    19 //      The copyright notice above does not evidence any 
     18//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     19//      The copyright notice above does not evidence any
    2020//      actual or intended publication of such source code.
    2121
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_fline.S

    r06731d6 r42e243e  
    1616//                      All Rights Reserved
    1717//
    18 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    19 //      The copyright notice above does not evidence any 
     18//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     19//      The copyright notice above does not evidence any
    2020//      actual or intended publication of such source code.
    2121
     
    5555        movel   #4,%d0
    5656        addl    #4,%a6          //to offset the sub.l #4,a7 above so that
    57 //                              ;a6 can point correctly to the stack frame 
     57//                              ;a6 can point correctly to the stack frame
    5858//                              ;before branching to mem_read
    5959        bsrl    mem_read
     
    6565        bfextu  %d0{#16:#6},%d1
    6666        cmpib   #0x17,%d1               //check if it is an FMOVECR encoding
    67         bne     not_mvcr       
     67        bne     not_mvcr
    6868//                              ;if an FMOVECR instruction, fix stack
    6969//                              ;and go to FPSP_UNIMP
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_operr.S

    r06731d6 r42e243e  
    1616// integer overflow, or the source op is inf, then the result stored is
    1717// garbage.
    18 // There are three cases in which operr is incorrectly signaled on the 
    19 // 040.  This occurs for move_out of format b, w, or l for the largest 
     18// There are three cases in which operr is incorrectly signaled on the
     19// 040.  This occurs for move_out of format b, w, or l for the largest
    2020// negative integer (-2^7 for b, -2^15 for w, -2^31 for l).
    2121//
     
    3939// If the inst is move_out, then same as Note 1.
    4040// If the inst is not move_out, the dest is not modified.
    41 // The exceptional operand is not defined for integer overflow 
     41// The exceptional operand is not defined for integer overflow
    4242// during a move_out.
    4343//
     
    4646//                      All Rights Reserved
    4747//
    48 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    49 //      The copyright notice above does not evidence any 
     48//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     49//      The copyright notice above does not evidence any
    5050//      actual or intended publication of such source code.
    5151
     
    8080
    8181//
    82 // If the destination size is B,W,or L, the operr must be 
     82// If the destination size is B,W,or L, the operr must be
    8383// handled here.
    8484//
     
    9393
    9494//
    95 // The size is not B,W,or L, so the operr is handled by the 
     95// The size is not B,W,or L, so the operr is handled by the
    9696// kernel handler.  Set the operr bits and clean up, leaving
    97 // only the integer exception frame on the stack, and the 
     97// only the integer exception frame on the stack, and the
    9898// fpu in the original exceptional state.
    9999//
     
    114114        andib   #0xe0,%d0               //clr all but tag
    115115        cmpib   #0x60,%d0               //check for nan
    116         beq     operr_nan       
     116        beq     operr_nan
    117117        cmpil   #0x80000000,FPTEMP_LO(%a6) //test if ls lword is special
    118118        bnes    chklerr         //if not equal, check for incorrect operr
     
    161161        andib   #0xe0,%d0               //clr all but tag
    162162        cmpib   #0x60,%d0               //check for nan
    163         beq     operr_nan       
     163        beq     operr_nan
    164164        cmpil   #0xffff8000,FPTEMP_LO(%a6) //test if ls lword is special
    165165        bnes    chkwerr         //if not equal, check for incorrect operr
     
    188188        andib   #0xe0,%d0               //clr all but tag
    189189        cmpib   #0x60,%d0               //check for nan
    190         beqs    operr_nan       
     190        beqs    operr_nan
    191191        cmpil   #0xffffff80,FPTEMP_LO(%a6) //test if ls lword is special
    192192        bnes    chkberr         //if not equal, check for incorrect operr
     
    232232        bclrb   #ainex_bit,FPSR_AEXCEPT(%a6)
    233233        fmovel  #0,%FPSR
    234        
     234
    235235        tstw    FPTEMP_EX(%a6)  //check sign
    236236        blts    load_neg
     
    283283        rts
    284284//
    285 // Check the exponent for $c000 and the upper 32 bits of the 
     285// Check the exponent for $c000 and the upper 32 bits of the
    286286// mantissa for $ffffffff.  If both are true, return d0 clr
    287287// and store the lower n bits of the least lword of FPTEMP
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_ovfl.S

    r06731d6 r42e243e  
    1111//      data register are too large to be represented in the
    1212//      destination format.
    13 //             
     13//
    1414// Trap disabled results
    1515//
     
    3838//                      All Rights Reserved
    3939//
    40 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    41 //      The copyright notice above does not evidence any 
     40//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     41//      The copyright notice above does not evidence any
    4242//      actual or intended publication of such source code.
    4343
     
    7676//
    7777        btstb   #ovfl_bit,FPCR_ENABLE(%a6)
    78         beqs    ck_inex 
     78        beqs    ck_inex
    7979//
    8080        btstb           #E3,E_BYTE(%a6)
     
    123123        unlk            %a6
    124124        bral            real_inex
    125        
     125
    126126ovfl_exit:
    127127        bclrb   #E3,E_BYTE(%a6) //test and clear E3 bit
     
    155155ovf_adj:
    156156//
    157 // Have a0 point to the correct operand. 
     157// Have a0 point to the correct operand.
    158158//
    159159        btstb   #E3,E_BYTE(%a6) //test E3 bit
     
    181181        moveb   L_SCR1(%a6),FPSR_CC(%a6)
    182182        bral    store           //stores to memory or register
    183        
     183
    184184not_opc011:
    185185        bsrl    ovf_r_x2        //returns a0 pointing to result
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_snan.S

    r06731d6 r42e243e  
    1717//
    1818// For trap enabled the 040 does the following:
    19 // If the inst is move_out, then the results are the same as for trap 
     19// If the inst is move_out, then the results are the same as for trap
    2020// disabled with the exception posted.  If the instruction is not move_
    2121// out, the dest. is not modified, and the exception is posted.
     
    2525//                      All Rights Reserved
    2626//
    27 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    28 //      The copyright notice above does not evidence any 
     27//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     28//      The copyright notice above does not evidence any
    2929//      actual or intended publication of such source code.
    3030
     
    142142
    143143//
    144 // Move_out 
     144// Move_out
    145145//
    146146move_out:
     
    150150        cmpil           #0,%d0          //check for long
    151151        beqs            sto_long        //branch if move_out long
    152        
     152
    153153        cmpil           #4,%d0          //check for word
    154154        beqs            sto_word        //branch if move_out word
    155        
     155
    156156        cmpil           #6,%d0          //check for byte
    157157        beqs            sto_byte        //branch if move_out byte
    158        
     158
    159159//
    160160// Not byte, word or long
    161161//
    162162        rts
    163 //     
     163//
    164164// Get the 32 most significant bits of etemp mantissa
    165165//
     
    170170// Set signalling nan bit
    171171//
    172         bsetl           #30,%d1                 
     172        bsetl           #30,%d1
    173173//
    174174// Store to the users destination address
     
    176176        tstl            %a0             //check if <ea> is 0
    177177        beqs            wrt_dn          //destination is a data register
    178        
     178
    179179        movel           %d1,-(%a7)      //move the snan onto the stack
    180180        movel           %a0,%a1         //load dest addr into a1
     
    192192// Set signalling nan bit
    193193//
    194         bsetl           #30,%d1                 
     194        bsetl           #30,%d1
    195195//
    196196// Store to the users destination address
     
    214214// Set signalling nan bit
    215215//
    216         bsetl           #30,%d1                 
     216        bsetl           #30,%d1
    217217//
    218218// Store to the users destination address
     
    256256//
    257257not_out:
    258         movel           DTAG(%a6),%d0   
     258        movel           DTAG(%a6),%d0
    259259        bfextu          %d0{#0:#3},%d0  //isolate dtag in lsbs
    260260
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_store.S

    r06731d6 r42e243e  
    1414//                      All Rights Reserved
    1515//
    16 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    17 //      The copyright notice above does not evidence any 
     16//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     17//      The copyright notice above does not evidence any
    1818//      actual or intended publication of such source code.
    1919
     
    5757//      handlers restore fp0-fp3 from there.
    5858//
    59         cmpb    #0x80,%d0               
     59        cmpb    #0x80,%d0
    6060        bnes    not_fp0
    6161        fmovemx %fp0-%fp0,USER_FP0(%a6)
     
    140140        swap    %d0             //d0 now in upper word
    141141        lsll    #4,%d0          //d0 now in proper place for dbl prec exp
    142         tstb    LOCAL_SGN(%a1) 
     142        tstb    LOCAL_SGN(%a1)
    143143        beqs    get_mant        //if positive, go process mantissa
    144144        bsetl   #31,%d0         //if negative, put in sign information
     
    211211        swap    %d0             //put exp in upper word of d0
    212212        lsll    #7,%d0          //shift it into single exp bits
    213         tstb    LOCAL_SGN(%a1) 
     213        tstb    LOCAL_SGN(%a1)
    214214        beqs    get_sman        //if positive, continue
    215215        bsetl   #31,%d0         //if negative, put in sign first
     
    243243        bral    reg_dest        //size is X, rts in reg_dest will
    244244//                              ;return to caller of dest_sgl
    245        
     245
    246246dest_ext:
    247247        tstb    LOCAL_SGN(%a1)  //put back sign into exponent word
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_unfl.S

    r06731d6 r42e243e  
    77//
    88// Trap disabled results
    9 //      For 881/2 compatibility, sw must denormalize the intermediate 
    10 // result, then store the result.  Denormalization is accomplished 
    11 // by taking the intermediate result (which is always normalized) and 
    12 // shifting the mantissa right while incrementing the exponent until 
    13 // it is equal to the denormalized exponent for the destination 
    14 // format.  After denormalization, the result is rounded to the 
     9//      For 881/2 compatibility, sw must denormalize the intermediate
     10// result, then store the result.  Denormalization is accomplished
     11// by taking the intermediate result (which is always normalized) and
     12// shifting the mantissa right while incrementing the exponent until
     13// it is equal to the denormalized exponent for the destination
     14// format.  After denormalization, the result is rounded to the
    1515// destination format.
    16 //             
     16//
    1717// Trap enabled results
    18 //      All trap disabled code applies. In addition the exceptional 
    19 // operand needs to made available to the user with a bias of $6000 
     18//      All trap disabled code applies. In addition the exceptional
     19// operand needs to made available to the user with a bias of $6000
    2020// added to the exponent.
    2121//
     
    2424//                      All Rights Reserved
    2525//
    26 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    27 //      The copyright notice above does not evidence any 
     26//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     27//      The copyright notice above does not evidence any
    2828//      actual or intended publication of such source code.
    2929
     
    9494//
    9595// Inexact enabled and reported, and we must take an inexact exception
    96 //     
     96//
    9797take_inex:
    9898        btstb           #E3,E_BYTE(%a6)
     
    148148//                                      ;we need the RND_PREC in the
    149149//                                      ;upper word for round
    150         movew           #0,-(%a7)       
     150        movew           #0,-(%a7)
    151151        movew           %d0,-(%a7)      //copy RND_PREC to stack
    152152//
     
    202202//
    203203//
    204 // Perform Round       
     204// Perform Round
    205205//      Input:          a0 points to input operand
    206206//                      d0{31:29} has guard, round, sticky
     
    225225        tstb            %d0
    226226        beqs            ext_opc011      //If extended, do not subtract
    227 //                              ;If destination format is sgl/dbl, 
     227//                              ;If destination format is sgl/dbl,
    228228        tstb            LOCAL_HI(%a0)   //If rounded result is normal,don't
    229229//                                      ;subtract
     
    260260
    261261//
    262 // Finish. 
     262// Finish.
    263263//
    264264unf_done:
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_unimp.S

    r06731d6 r42e243e  
    44//      x_unimp.sa 3.3 7/1/91
    55//
    6 //      fpsp_unimp --- FPSP handler for unimplemented instruction       
     6//      fpsp_unimp --- FPSP handler for unimplemented instruction
    77//      exception.
    88//
     
    1111// (See table 8-1 MC68030 User's Manual).
    1212//
    13 // 
     13//
    1414// Note: An fsave for an unimplemented inst. will create a short
    1515// fsave stack.
     
    2525//                      All Rights Reserved
    2626//
    27 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    28 //      The copyright notice above does not evidence any 
     27//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     28//      The copyright notice above does not evidence any
    2929//      actual or intended publication of such source code.
    3030
  • c/src/lib/libcpu/m68k/m68040/fpsp/x_unsupp.S

    r06731d6 r42e243e  
    66//      fpsp_unsupp --- FPSP handler for unsupported data type exception
    77//
    8 // Trap vector #55      (See table 8-1 Mc68030 User's manual). 
     8// Trap vector #55      (See table 8-1 Mc68030 User's manual).
    99// Invoked when the user program encounters a data format (packed) that
    1010// hardware does not support or a data type (denormalized numbers or un-
    1111// normalized numbers).
    12 // Normalizes denorms and unnorms, unpacks packed numbers then stores 
    13 // them back into the machine to let the 040 finish the operation. 
     12// Normalizes denorms and unnorms, unpacks packed numbers then stores
     13// them back into the machine to let the 040 finish the operation.
    1414//
    1515// Unsupp calls two routines:
     
    2626//                      All Rights Reserved
    2727//
    28 //      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 
    29 //      The copyright notice above does not evidence any 
     28//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
     29//      The copyright notice above does not evidence any
    3030//      actual or intended publication of such source code.
    3131
  • cpukit/score/cpu/bfin/irq.c

    r06731d6 r42e243e  
    1111 *  $Id$
    1212 */
    13  
     13
    1414
    1515#if 0 /* this file no longer used */
    16  
     16
    1717#include <rtems/system.h>
    1818#include <rtems/score/cpu.h>
  • cpukit/score/cpu/bfin/rtems/score/bfin.h

    r06731d6 r42e243e  
    11/*  bfin.h
    22 *
    3  *  This file sets up basic CPU dependency settings based on 
     3 *  This file sets up basic CPU dependency settings based on
    44 *  compiler settings.  For example, it can determine if
    55 *  floating point is available.  This particular implementation
     
    3939 *  to.
    4040 */
    41  
     41
    4242/*
    43  *  Figure out all CPU Model Feature Flags based upon compiler 
    44  *  predefines. 
     43 *  Figure out all CPU Model Feature Flags based upon compiler
     44 *  predefines.
    4545 */
    4646#if defined(__BFIN__)
     
    4848#define BF_HAS_FPU   0
    4949#else
    50  
     50
    5151#error "Unsupported CPU Model"
    52  
     52
    5353#endif
    5454
     
    5656 *  Define the name of the CPU family.
    5757 */
    58  
     58
    5959#define CPU_NAME "BFIN"
    6060
  • cpukit/score/cpu/bfin/rtems/score/cpu.h

    r06731d6 r42e243e  
    66 *  This include file contains information pertaining to the Blackfin
    77 *  processor.
    8  * 
     8 *
    99 *  COPYRIGHT (c) 1989-2006.
    1010 *  On-Line Applications Research Corporation (OAR).
     
    170170/**
    171171 *  Does the RTEMS invoke the user's ISR with the vector number and
    172  *  a pointer to the saved interrupt frame (1) or just the vector 
     172 *  a pointer to the saved interrupt frame (1) or just the vector
    173173 *  number (0)?
    174174 *
     
    197197 */
    198198
    199 /** 
     199/**
    200200 *  @def CPU_SOFTWARE_FP
    201201 *
     
    205205 *
    206206 *  This feature conditional is used to indicate whether or not there
    207  *  is software implemented floating point that must be context 
     207 *  is software implemented floating point that must be context
    208208 *  switched.  The determination of whether or not this applies
    209209 *  is very tool specific and the state saved/restored is also
     
    357357 *  XXX document implementation including references if appropriate
    358358 */
    359 #define CPU_STRUCTURE_ALIGNMENT 
     359#define CPU_STRUCTURE_ALIGNMENT
    360360
    361361/**
     
    478478    uint32_t   register_p3;
    479479    uint32_t   register_p4;
    480     uint32_t   register_p5;                         
     480    uint32_t   register_p5;
    481481    uint32_t   register_fp;
    482482    uint32_t   register_sp;
    483    
     483
    484484    uint32_t   register_l0;
    485485    uint32_t   register_l1;
    486486    uint32_t   register_l2;
    487     uint32_t   register_l3;   
    488    
     487    uint32_t   register_l3;
     488
    489489    uint32_t   register_rets;
    490490
    491     uint32_t   imask; 
     491    uint32_t   imask;
    492492} Context_Control;
    493493
     
    512512 */
    513513typedef struct {
    514     /** This field is a hint that a port will have a number of integer 
     514    /** This field is a hint that a port will have a number of integer
    515515     *  registers that need to be saved when an interrupt occurs or
    516516     *  when a context switch occurs at the end of an ISR.
     
    552552/**
    553553 *  @ingroup CPUInterrupt
    554  *  This variable points to the lowest physical address of the interrupt 
     554 *  This variable points to the lowest physical address of the interrupt
    555555 *  stack.
    556556 */
     
    559559/**
    560560 *  @ingroup CPUInterrupt
    561  *  This variable points to the lowest physical address of the interrupt 
     561 *  This variable points to the lowest physical address of the interrupt
    562562 *  stack.
    563563 */
     
    653653 *  @note  This does not have to be a power of 2 although it should be
    654654 *         a multiple of 2 greater than or equal to 2.  The requirement
    655  *         to be a multiple of 2 is because the heap uses the least 
     655 *         to be a multiple of 2 is because the heap uses the least
    656656 *         significant field of the front and back flags to indicate
    657657 *         that a block is in use or free.  So you do not want any odd
     
    730730       asm volatile ("cli %0; csync \n" : "=d" (_level) );     \
    731731  }
    732  
     732
    733733
    734734/**
     
    942942 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
    943943 *
    944  *  This set of routines are used to implement fast searches for 
     944 *  This set of routines are used to implement fast searches for
    945945 *  the most important ready task.
    946946 */