Changeset 7c4c284c in rtems


Ignore:
Timestamp:
Apr 14, 2009, 1:44:29 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
af86b82
Parents:
67ae7bb6
Message:

2009-04-14 Michael Walle <michael@…>

  • cpu.h: corrected the registers in Context_Control and in CPU_Interrupt_frame to correspond to the saved frame in cpu_asm.S

Also switched on CPU_ISR_PASSES_FRAME_POINTER.

  • cpu_asm.S: Moved the restore part of _CPU_Context_switch for

easier reading. Fixed _CPU_Context_restore, it now moves the
argument and branches to a label in _CPU_Context_switch. Removed
unnecessary saves of registers in context switch and irq handling.
Rewrote irq code to call the C helper. Added some documentation

  • irq.c: New file derived from c4x and nios2.
Location:
cpukit/score/cpu/lm32
Files:
1 added
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/lm32/ChangeLog

    r67ae7bb6 r7c4c284c  
     12009-04-14      Michael Walle <michael@walle.cc>
     2
     3        * cpu.h: corrected the registers in Context_Control and
     4        in CPU_Interrupt_frame to correspond to the saved frame in cpu_asm.S
     5        Also switched on CPU_ISR_PASSES_FRAME_POINTER.
     6        * cpu_asm.S: Moved the restore part of _CPU_Context_switch for
     7        easier reading.  Fixed _CPU_Context_restore, it now moves the
     8        argument and branches to a label in _CPU_Context_switch.  Removed
     9        unnecessary saves of registers in context switch and irq handling.
     10        Rewrote irq code to call the C helper.  Added some documentation
     11        * irq.c: New file derived from c4x and nios2.
     12
    1132009-04-06      Michael Walle <michael@walle.cc>
    214
  • cpukit/score/cpu/lm32/Makefile.am

    r67ae7bb6 r7c4c284c  
    1313
    1414noinst_LIBRARIES = libscorecpu.a
    15 libscorecpu_a_SOURCES = cpu.c cpu_asm.S
     15libscorecpu_a_SOURCES = cpu.c cpu_asm.S irq.c
    1616libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
    1717
  • cpukit/score/cpu/lm32/cpu_asm.S

    r67ae7bb6 r7c4c284c  
    1414 *  Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
    1515 *  Micro-Research Finland Oy
     16 *
     17 *  Michael Walle <michael@walle.cc>, 2009
    1618 */
    1719
     
    1921#include <rtems/score/cpu_asm.h>
    2022
    21 #define MICO32_FULL_CONTEXT_SAVE_RESTORE
    22        
    2323/*  void _CPU_Context_switch(run_context, heir_context)
    2424 *
     
    2727 *  LM32 Specific Information:
    2828 *
    29  *  XXX document implementation including references if appropriate
     29 *  Saves/restores all callee-saved general purpose registers as well as
     30 *  the stack pointer, return address and interrupt enable status register
     31 *  to/from the context.
     32 *
    3033 */
    3134    .globl _CPU_Context_switch
    3235_CPU_Context_switch:
    33     sw      (r1+0), r9
    34     sw      (r1+4), r10
    35     sw      (r1+8), r11
    36     sw      (r1+12), r12
    37     sw      (r1+16), r13
    38     sw      (r1+20), r14
    39     sw      (r1+24), r15
    40     sw      (r1+28), r16
    41     sw      (r1+32), r17
    42     sw      (r1+36), r18
    43     sw      (r1+40), r19
    44     sw      (r1+44), r20
    45     sw      (r1+48), r21
    46     sw      (r1+52), r22
    47     sw      (r1+56), r23
    48     sw      (r1+60), r24
    49     sw      (r1+64), r25
    50     sw      (r1+68), gp
    51     sw      (r1+72), fp
    52     sw      (r1+76), sp
    53     sw      (r1+80), ra
     36    sw      (r1+0), r11   /* r1 is the first argument */
     37    sw      (r1+4), r12
     38    sw      (r1+8), r13
     39    sw      (r1+12), r14
     40    sw      (r1+16), r15
     41    sw      (r1+20), r16
     42    sw      (r1+24), r17
     43    sw      (r1+28), r18
     44    sw      (r1+32), r19
     45    sw      (r1+36), r20
     46    sw      (r1+40), r21
     47    sw      (r1+44), r22
     48    sw      (r1+48), r23
     49    sw      (r1+52), r24
     50    sw      (r1+56), r25
     51    sw      (r1+60), gp
     52    sw      (r1+64), fp
     53    sw      (r1+68), sp
     54    sw      (r1+72), ra
     55    rcsr    r3, IE
     56    sw      (r1+76), r3
     57_CPU_Context_switch_restore:
     58    lw      r11, (r2+0)   /* r2 is the second argument */
     59    lw      r12, (r2+4)
     60    lw      r13, (r2+8)
     61    lw      r14, (r2+12)
     62    lw      r15, (r2+16)
     63    lw      r16, (r2+20)
     64    lw      r17, (r2+24)
     65    lw      r18, (r2+28)
     66    lw      r19, (r2+32)
     67    lw      r20, (r2+36)
     68    lw      r21, (r2+40)
     69    lw      r22, (r2+44)
     70    lw      r23, (r2+48)
     71    lw      r24, (r2+52)
     72    lw      r25, (r2+56)
     73    lw      gp, (r2+60)
     74    lw      fp, (r2+64)
     75    lw      sp, (r2+68)
     76    lw      ra, (r2+72)
     77    lw      r3, (r2+76)
     78    wcsr    IE, r3
     79    ret
    5480
    5581/*
     
    5985 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
    6086 *
    61  *  NOTE: May be unnecessary to reload some registers.
    62  *
    6387 *  LM32 Specific Information:
    6488 *
    65  *  XXX document implementation including references if appropriate
     89 *  Moves argument #1 to #2 and branches to the restore part of the
     90 *  context switch code above.
    6691 */
    6792    .globl _CPU_Context_restore
    6893_CPU_Context_restore:
    69     lw      r9, (r2+0)
    70     lw      r10, (r2+4)
    71     lw      r11, (r2+8)
    72     lw      r12, (r2+12)
    73     lw      r13, (r2+16)
    74     lw      r14, (r2+20)
    75     lw      r15, (r2+24)
    76     lw      r16, (r2+28)
    77     lw      r17, (r2+32)
    78     lw      r18, (r2+36)
    79     lw      r19, (r2+40)
    80     lw      r20, (r2+44)
    81     lw      r21, (r2+48)
    82     lw      r22, (r2+52)
    83     lw      r23, (r2+56)
    84     lw      r24, (r2+60)
    85     lw      r25, (r2+64)
    86     lw      gp, (r2+68)
    87     lw      fp, (r2+72)
    88     lw      ra, (r2+80)
    89     /* Stack pointer must be restored last, in case it has been updated */
    90     lw      sp, (r2+76)
    91     nop
    92     ret
    93        
    94 /*  void __ISR_Handler()
     94    mv      r2, r1
     95    bi      _CPU_Context_switch_restore
     96   
     97/*  void _ISR_Handler()
    9598 *
    9699 *  This routine provides the RTEMS interrupt management.
     
    98101 *  LM32 Specific Information:
    99102 *
    100  *  XXX document implementation including references if appropriate
     103 *  Saves all the caller-saved general purpose registers as well as the
     104 *  return address, exception return address and breakpoint return address
     105 *  (the latter may be unnecessary) onto the stack, which is either the task
     106 *  stack (in case of a interrupted task) or the interrupt stack (if an
     107 *  interrupt was interrupted).
     108 *  After that, it figures out the pending interrupt with the highest
     109 *  priority and calls the main ISR handler written in C, which in turn
     110 *  handles interrupt nesting, software interrupt stack setup etc and
     111 *  finally calls the user ISR.
     112 *  At the end the saved registers are restored.
     113 * 
    101114 */
    102115
    103116    .globl  _ISR_Handler
    104117_ISR_Handler:
    105     xor     r0, r0, r0
    106     addi    sp, sp, -128
    107     sw      (sp+4), r1
    108     sw      (sp+8), r2
    109     sw      (sp+12), r3
    110     sw      (sp+16), r4
    111     sw      (sp+20), r5
    112     sw      (sp+24), r6
    113     sw      (sp+28), r7
    114     sw      (sp+32), r8
    115     sw      (sp+36), r9
    116     sw      (sp+40), r10
    117 #ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
    118     sw      (sp+44), r11
    119     sw      (sp+48), r12
    120     sw      (sp+52), r13
    121     sw      (sp+56), r14
    122     sw      (sp+60), r15
    123     sw      (sp+64), r16
    124     sw      (sp+68), r17
    125     sw      (sp+72), r18
    126     sw      (sp+76), r19
    127     sw      (sp+80), r20
    128     sw      (sp+84), r21
    129     sw      (sp+88), r22
    130     sw      (sp+92), r23
    131     sw      (sp+96), r24
    132     sw      (sp+100), r25
    133     sw      (sp+104), r26
    134     sw      (sp+108), r27
    135 #endif
    136     sw      (sp+116), ra
    137     sw      (sp+120), ea
    138     sw      (sp+124), ba
     118    xor      r0, r0, r0
     119    addi     sp, sp, -52
     120    sw       (sp+4), r1
     121    sw       (sp+8), r2
     122    sw       (sp+12), r3
     123    sw       (sp+16), r4
     124    sw       (sp+20), r5
     125    sw       (sp+24), r6
     126    sw       (sp+28), r7
     127    sw       (sp+32), r8
     128    sw       (sp+36), r9
     129    sw       (sp+40), r10
     130    sw       (sp+44), ra
     131    sw       (sp+48), ea
     132    sw       (sp+52), ba
    139133
    140     /* Scan through (IP & IM) bits starting from LSB until irq found */
    141     rcsr    r2,IP
    142     rcsr    r3,IM
    143     and     r4,r2,r3
    144     or      r1,r0,r0
    145     ori     r5,r0,1
    146 find_irq:       
    147     and     r6,r4,r5
    148     bne     r6,r0,found_irq
    149     sli     r5,r5,1
    150     addi    r1,r1,1
    151     bne     r5,r0,find_irq
    152     /* If we end up here there was no interrupt - this should never
    153        happen! */
    154     bi      exit_isr
     134    /*
     135     * Scan through IP & IM bits starting from LSB until irq vector is
     136     * found. The vector is stored in r1, which is the first argument for
     137     * __ISR_Handler.
     138     */
     139    rcsr    r2, IP
     140    rcsr    r3, IM
     141    mv      r1, r0        /* r1: counter for the vector number */
     142    and     r2, r2, r3    /* r2: pending irqs, which are enabled */
     143    mvi     r3, 1         /* r3: register for the walking 1 */
     144    /*
     145     * If r2 is zero, there was no interrupt.
     146     * This should never happen!
     147     */
     148    be      r2, r0, exit_isr
     149find_irq:
     150    and     r4, r2, r3
     151    bne     r4, r0, found_irq
     152    sli     r3, r3, 1
     153    addi    r1, r1, 1
     154    bi      find_irq
    155155
    156156found_irq:
    157     .extern _ISR_Vector_table
    158     sli     r1,r1,2
    159     mvhi    r7,hi(_ISR_Vector_table)
    160     ori     r7,r7,lo(_ISR_Vector_table)
    161     lw      r6,(r7+0)
    162     add     r6,r6,r1
    163     lw      r5,(r6+0)
    164     call    r5
     157    /*
     158     * Call __ISR_Handler for further processing.
     159     * r1 is the vector number, calculated above
     160     * r2 is the pointer to the CPU_Interrupt_frame
     161     */
     162    addi    r2, sp, 4
    165163
     164    .extern __ISR_Handler
     165    mvhi    r3, hi(__ISR_Handler)
     166    ori     r3, r3, lo(__ISR_Handler)
     167    call    r3
     168   
    166169exit_isr:
     170    /* Restore the saved registers */
    167171    lw      r1, (sp+4)
    168172    lw      r2, (sp+8)
     
    175179    lw      r9, (sp+36)
    176180    lw      r10, (sp+40)
    177 #ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
    178     lw      r11, (sp+44)
    179     lw      r12, (sp+48)
    180     lw      r13, (sp+52)
    181     lw      r14, (sp+56)
    182     lw      r15, (sp+60)
    183     lw      r16, (sp+64)
    184     lw      r17, (sp+68)
    185     lw      r18, (sp+72)
    186     lw      r19, (sp+76)
    187     lw      r20, (sp+80)
    188     lw      r21, (sp+84)
    189     lw      r22, (sp+88)
    190     lw      r23, (sp+92)
    191     lw      r24, (sp+96)
    192     lw      r25, (sp+100)
    193     lw      r26, (sp+104)
    194     lw      r27, (sp+108)
    195 #endif
    196     lw      ra, (sp+116)
    197     lw      ea, (sp+120)
    198     lw      ba, (sp+124)
    199     addi    sp, sp, 128
    200     nop
     181    lw      ra, (sp+44)
     182    lw      ea, (sp+48)
     183    lw      ba, (sp+52)
     184    addi    sp, sp, 52
    201185    eret
    202186
  • cpukit/score/cpu/lm32/rtems/score/cpu.h

    r67ae7bb6 r7c4c284c  
    176176 *  XXX document implementation including references if appropriate
    177177 */
    178 #define CPU_ISR_PASSES_FRAME_POINTER 0
     178#define CPU_ISR_PASSES_FRAME_POINTER 1
    179179
    180180/**
     
    463463 */
    464464typedef struct {
    465   uint32_t r9;
    466   uint32_t r10;
    467465  uint32_t r11;
    468466  uint32_t r12;
     
    484482  uint32_t sp;
    485483  uint32_t ra;
     484  uint32_t ie;
    486485} Context_Control;
    487486
     
    521520  uint32_t r7;
    522521  uint32_t r8;
     522  uint32_t r9;
     523  uint32_t r10;
    523524  uint32_t ra;
    524   uint32_t gp;
    525525  uint32_t ba;
     526  uint32_t ea;
    526527} CPU_Interrupt_frame;
    527528
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