#2023 closed defect (fixed)

A generic BSP for the Xilinx Virtex 5 (PPC 440)

Reported by: Ric Claus Owned by: Sebastian Huber
Priority: normal Milestone: 4.11
Component: bsps Version: 4.10
Severity: normal Keywords:
Cc: joel.sherrill@…, sebastian.huber@…, claus@… Blocked By:
Blocking:

Description

Like the Virtex 4 BSP previously submitted, this BSP makes no assumptions on what firmware is loaded into the FPGA.

Attachments (3)

0006-Virtex-5-BSP.patch (62.3 KB) - added by Ric Claus on Feb 17, 2012 at 10:09:18 PM.
Basic patch that unfortunately includes some irrelevant files
0007-Virtex-5-BSP.patch (2.1 KB) - added by Ric Claus on Feb 17, 2012 at 10:09:47 PM.
Patch to get rid of the aforementioned irrelevant files
0014-Fixes-updates-and-improvements-to-virtex5-BSP.patch (28.2 KB) - added by Ric Claus on Mar 2, 2012 at 1:01:09 AM.
Various fixes to the virtex5 BSP

Download all attachments as: .zip

Change History (7)

Changed on Feb 17, 2012 at 10:09:18 PM by Ric Claus

Attachment: 0006-Virtex-5-BSP.patch added

Basic patch that unfortunately includes some irrelevant files

Changed on Feb 17, 2012 at 10:09:47 PM by Ric Claus

Attachment: 0007-Virtex-5-BSP.patch added

Patch to get rid of the aforementioned irrelevant files

comment:1 Changed on Feb 18, 2012 at 5:24:25 PM by Ric Claus

Cc: Ric Claus added

comment:2 Changed on Feb 20, 2012 at 7:12:36 AM by Sebastian Huber

Cc: Sebastian Huber added
dependson: 2020
Owner: changed from Joel Sherrill to Sebastian Huber

comment:3 Changed on Feb 21, 2012 at 6:07:59 PM by Joel Sherrill

Cc: Joel Sherrill added

Changed on Mar 2, 2012 at 1:01:09 AM by Ric Claus

Various fixes to the virtex5 BSP

comment:4 Changed on Mar 30, 2012 at 2:17:02 PM by Joel Sherrill

Resolution: fixed
Status: newclosed

Merged onto upstream master

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