Ticket #2023: 0006-Virtex-5-BSP.patch

new file c/src/lib/libbsp/powerpc/virtex5/ChangeLog

@@ +1 @@
+2011-03-4       Ric Claus <claus@slac.stanford.edu>
+
+        * ChangeLog, virtex5.cfg: added files.

new file c/src/lib/libbsp/powerpc/virtex5/Makefile.am

@@ +1 @@
+##
+## $Id: $
+##
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+
+include_bspdir = $(includedir)/bsp
+
+dist_project_lib_DATA = bsp_specs
+
+# include
+include_HEADERS  = include/bsp.h
+#include_HEADERS += include/tm27.h
+
+nodist_include_HEADERS     = include/bspopts.h
+nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
+DISTCLEANFILES             = include/bspopts.h
+
+nodist_include_HEADERS += include/coverhd.h
+
+# start
+noinst_LIBRARIES      = libbspstart.a
+libbspstart_a_SOURCES = ../../powerpc/shared/start/rtems_crti.S
+project_lib_DATA      = rtems_crti.$(OBJEXT)
+
+dist_project_lib_DATA += startup/linkcmds
+
+noinst_LIBRARIES += libbsp.a
+
+# startup
+libbsp_a_SOURCES = startup/bspclean.c \
+                   ../shared/startup/zerobss.c \
+                   ../../shared/bsplibc.c \
+                   ../../shared/bspgetworkarea.c \
+                   ../../shared/bsppost.c \
+                   startup/bspstart.c \
+                   ../../shared/bootcard.c \
+                   ../../shared/sbrk.c \
+                   ../../shared/gnatinstallhandler.c
+
+# start
+libbsp_a_SOURCES += startup/start.S
+
+# clock
+libbsp_a_SOURCES += ../shared/clock/clock.c
+
+# console
+libbsp_a_SOURCES += startup/dummy_console.c \
+                    ../../shared/dummy_printk_support.c
+
+# irq
+include_bsp_HEADERS = include/irq.h
+
+#vectors
+include_bsp_HEADERS += ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h
+include_bsp_HEADERS += ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
+                  ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
+                  ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
+                  ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
+                  ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel
+
+EXTRA_DIST =
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../../automake/local.am

new file c/src/lib/libbsp/powerpc/virtex5/bsp_specs

@@ +1 @@
+%rename startfile old_startfile
+%rename link      old_link
+%rename endfile   old_endfile
+
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems:  ecrti%O%s rtems_crti%O%s crtbegin.o%s }}
+
+*link:
+%{!qrtems: %(old_link)} \
+%{qrtems: -dc -dp -Bstatic -u __vectors -u download_entry -N }
+
+*endfile:
+%{!qrtems: %(old_endfile)} \
+%{qrtems: crtend.o%s ecrtn.o%s}

new file c/src/lib/libbsp/powerpc/virtex5/configure.ac

@@ +1 @@
+dnl Process this file with autoconf to produce a configure script.
+dnl
+dnl $Id: $
+
+AC_PREREQ(2.68)
+AC_INIT([rtems-c-src-lib-libbsp-powerpc-virtex5],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_CHECK_NETWORKING
+
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+
+RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[1])
+RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
+[If defined, then the PowerPC specific code in RTEMS will use some
+ of the special purpose registers to slightly optimize interrupt
+ response time.  The use of these registers can conflict with
+ other tools like debuggers.])
+
+RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
+RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
+[This defines the base address of the exception table.])
+
+RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
+
+# Explicitly list all Makefiles here
+AC_CONFIG_FILES([Makefile])
+
+RTEMS_PPC_EXCEPTIONS
+
+AC_OUTPUT

new file c/src/lib/libbsp/powerpc/virtex5/include/bsp.h

@@ +1 @@
+/*  bsp.h
+ *
+ *  This include file contains all GEN405 board IO definitions.
+ *
+ * derived from helas403/include/bsp.h:
+ *  Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp
+ *  Author:     Thomas Doerfler <td@imd.m.isar.de>
+ *              IMD Ingenieurbuero fuer Microcomputertechnik
+ *
+ *  COPYRIGHT (c) 1998 by IMD
+ *
+ *  Changes from IMD are covered by the original distributions terms.
+ *  This file has been derived from the papyrus BSP.
+ *
+ *  Author:     Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id: bsp.h 63 2011-04-26 00:23:51Z claus $
+ *
+ */
+
+#ifndef _BSP_H
+#define _BSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bspopts.h>
+
+/*
+ *  confdefs.h overrides for this BSP:
+ *   - Interrupt stack space is not minimum if defined.
+ */
+
+#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
+
+#ifdef ASM
+/* Definition of where to store registers in alignment handler */
+#define ALIGN_REGS 0x0140
+
+#else
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+#include <rtems/iosupp.h>
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

new file c/src/lib/libbsp/powerpc/virtex5/include/bspopts.h.in~

@@ +1 @@
+/* include/bspopts.h.in.  Generated from configure.ac by autoheader.  */
+
+/* If defined, then the BSP Framework will put a non-zero pattern into the
+   RTEMS Workspace and C program heap. This should assist in finding code that
+   assumes memory starts set to zero. */
+#undef BSP_DIRTY_MEMORY
+
+/* If defined, print a message and wait until pressed before resetting board
+   when application exits. */
+#undef BSP_PRESS_KEY_FOR_RESET
+
+/* If defined, reset the board when the application exits. */
+#undef BSP_RESET_BOARD_AT_EXIT
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* If defined, then the PowerPC specific code in RTEMS will use some of the
+   special purpose registers to slightly optimize interrupt response time. The
+   use of these registers can conflict with other tools like debuggers. */
+#undef PPC_USE_SPRG
+
+/* This defines the base address of the exception table. NOTE: Vectors are
+   actually at 0xFFF00000 but file starts at offset. */
+#undef PPC_VECTOR_FILE_BASE

new file c/src/lib/libbsp/powerpc/virtex5/include/coverhd.h

@@ +1 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C.  These are used in the
+ *  Timing Test Suite to ignore the overhead required to pass arguments
+ *  to directives.  On some CPUs and/or target boards, this overhead
+ *  is significant and makes it difficult to distinguish internal
+ *  RTEMS execution time from that used to call the directive.
+ *  This file should be updated after running the C overhead timing
+ *  test.  Once this update has been performed, the RTEMS Time Test
+ *  Suite should be rebuilt to account for these overhead times in the
+ *  timing results.
+ *
+ *  NOTE:  If these are all zero, then the times reported include
+ *         all calling overhead including passing of arguments.
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id: coverhd.h 63 2011-04-26 00:23:51Z claus $
+ */
+
+/*
+ *  Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  Units are 100ns.
+ *
+ *  These numbers are of questionable use, as they are developed by calling
+ *  the routine many times, thus getting its entry veneer into the (small)
+ *  cache on the 403GA.  This in general is not true of the RTEMS timing
+ *  tests, which usually call a routine only once, thus having no cache loaded
+ *  advantage.
+ *
+ *  Whether the directive times are useful after deducting the function call
+ *  overhead is also questionable.  The user is more interested generally
+ *  in the total cost of a directive, not the cost if the procedure call
+ *  is inlined!  (In general this is not true).
+ *
+ *  Andrew Bray 18/08/1995
+ *
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      1
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        1
+#define CALLING_OVERHEAD_TASK_CREATE               3
+#define CALLING_OVERHEAD_TASK_IDENT                1
+#define CALLING_OVERHEAD_TASK_START                1
+#define CALLING_OVERHEAD_TASK_RESTART              1
+#define CALLING_OVERHEAD_TASK_DELETE               1
+#define CALLING_OVERHEAD_TASK_SUSPEND              1
+#define CALLING_OVERHEAD_TASK_RESUME               1
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         1
+#define CALLING_OVERHEAD_TASK_MODE                 1
+#define CALLING_OVERHEAD_TASK_GET_NOTE             1
+#define CALLING_OVERHEAD_TASK_SET_NOTE             1
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            4
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           1
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           1
+#define CALLING_OVERHEAD_CLOCK_GET                 4
+#define CALLING_OVERHEAD_CLOCK_SET                 3
+#define CALLING_OVERHEAD_CLOCK_TICK                1
+
+#define CALLING_OVERHEAD_TIMER_CREATE              1
+#define CALLING_OVERHEAD_TIMER_IDENT               1
+#define CALLING_OVERHEAD_TIMER_DELETE              1
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          2
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           5
+#define CALLING_OVERHEAD_TIMER_RESET               1
+#define CALLING_OVERHEAD_TIMER_CANCEL              1
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          2
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           1
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          1
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          1
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      2
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   1
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     2
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       1
+
+#define CALLING_OVERHEAD_EVENT_SEND                1
+#define CALLING_OVERHEAD_EVENT_RECEIVE             2
+#define CALLING_OVERHEAD_SIGNAL_CATCH              1
+#define CALLING_OVERHEAD_SIGNAL_SEND               1
+#define CALLING_OVERHEAD_PARTITION_CREATE          3
+#define CALLING_OVERHEAD_PARTITION_IDENT           1
+#define CALLING_OVERHEAD_PARTITION_DELETE          1
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      1
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   1
+#define CALLING_OVERHEAD_REGION_CREATE             3
+#define CALLING_OVERHEAD_REGION_IDENT              1
+#define CALLING_OVERHEAD_REGION_DELETE             1
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        2
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     1
+#define CALLING_OVERHEAD_PORT_CREATE               2
+#define CALLING_OVERHEAD_PORT_IDENT                1
+#define CALLING_OVERHEAD_PORT_DELETE               1
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             2
+#define CALLING_OVERHEAD_IO_OPEN                   2
+#define CALLING_OVERHEAD_IO_CLOSE                  2
+#define CALLING_OVERHEAD_IO_READ                   2
+#define CALLING_OVERHEAD_IO_WRITE                  2
+#define CALLING_OVERHEAD_IO_CONTROL                2
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      1
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     1
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      1
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     1
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     1
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     1
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

new file c/src/lib/libbsp/powerpc/virtex5/include/irq.h

@@ +1 @@
+#ifndef VIRTEX5_RTEMSBSP_IRQ_H
+#define VIRTEX5_RTEMSBSP_IRQ_H
+
+#warning "virtex5 BSP's <bsp/irq.h> is BOGUS; this BSP implements no interrupt handling.  This header exists to get everything to compile."
+
+#define BSP_SHARED_HANDLER_SUPPORT 1
+
+#include <rtems/irq.h>
+
+#endif

new file c/src/lib/libbsp/powerpc/virtex5/make/custom/virtex5.cfg

@@ +1 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU=powerpc
+RTEMS_CPU_MODEL=ppc440
+
+#  This contains the compiler options necessary to select the CPU model
+#  and (hopefully) optimize for it.
+#
+CPU_CFLAGS = -mcpu=440 -Dppc440 -msoft-float
+
+# optimize flag: typically -O2
+CFLAGS_OPTIMIZE_V = -O2 -g -fno-keep-inline-functions
+
+# Miscellaneous additions go here
+define bsp-post-link
+        $(default-bsp-post-link)
+        $(OBJCOPY) -O srec $(basename $@).exe $(basename $@)$(DOWNEXT)
+endef
+

new file c/src/lib/libbsp/powerpc/virtex5/preinstall.am

@@ +1 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+        $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+all-local: $(TMPINSTALL_FILES)
+
+TMPINSTALL_FILES =
+CLEANFILES = $(TMPINSTALL_FILES)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES += $(PREINSTALL_FILES)
+
+$(PROJECT_LIB)/$(dirstamp):
+        @$(MKDIR_P) $(PROJECT_LIB)
+        @: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+        @$(MKDIR_P) $(PROJECT_INCLUDE)
+        @: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/bsp/$(dirstamp):
+        @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
+        @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
+
+$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+
+$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
+
+$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
+$(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
+
+$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
+

new file c/src/lib/libbsp/powerpc/virtex5/startup/bspclean.c

@@ +1 @@
+/*  bsp_cleanup()
+ *
+ *  This routine normally is part of start.s and usually returns
+ *  control to a monitor.
+ *
+ *  INPUT:  NONE
+ *
+ *  OUTPUT: NONE
+ *
+ *  Author:     Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspclean.c:
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id: bspclean.c 63 2011-04-26 00:23:51Z claus $
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+void bsp_cleanup( void )
+{
+  /*  rtems_fatal_error_occurred(0); */
+}

new file c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c

@@ +1 @@
+/*  bsp_start()
+ *
+ *  This routine starts the application.  It includes application,
+ *  board, and monitor specific initialization and configuration.
+ *  The generic CPU dependent initialization has been performed
+ *  before this routine is invoked.
+ *
+ *  INPUT:  NONE
+ *
+ *  OUTPUT: NONE
+ *
+ *  Author:     Thomas Doerfler <td@imd.m.isar.de>
+ *              IMD Ingenieurbuero fuer Microcomputertechnik
+ *
+ *  COPYRIGHT (c) 1998 by IMD
+ *
+ *  Changes from IMD are covered by the original distributions terms.
+ *  This file has been derived from the papyrus BSP:
+ *
+ *  Author:     Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Modifications for spooling console driver and control of memory layout
+ *  with linker command file by
+ *              Thomas Doerfler <td@imd.m.isar.de>
+ *  for these modifications:
+ *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies. IMD makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Modifications for PPC405GP by Dennis Ehlin
+ *  Modifications for Virtex5 by Richard Claus <claus@slac.stanford.edu>
+ *
+ *  $Id: bspstart.c 63 2011-04-26 00:23:51Z claus $
+ */
+
+#include <string.h>
+#include <fcntl.h>
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <rtems/libcsupport.h>
+#include <rtems/bspIo.h>
+#include <bsp/vectors.h>
+#include <libcpu/spr.h>
+#include <libcpu/cpuIdent.h>
+
+#define DO_DOWN_ALIGN(x,a) ((x) & ~((a)-1))
+
+#define DO_UP_ALIGN(x,a)   DO_DOWN_ALIGN(((x) + (a) - 1 ),a)
+
+#define CPU_DOWN_ALIGN(x)  DO_DOWN_ALIGN(x, CPU_ALIGNMENT)
+#define CPU_UP_ALIGN(x)    DO_UP_ALIGN(x, CPU_ALIGNMENT)
+
+
+/* Expected by clock.c */
+uint32_t    bsp_clicks_per_usec;
+bool        bsp_timer_internal_clock;   /* true, when timer runs with CPU clk */
+uint32_t    bsp_timer_least_valid;
+uint32_t    bsp_timer_average_overhead;
+
+
+/* Provide weak aliases so that RTEMS distribution builds; the
+ * generated executables are bogus, however...
+ */
+void __app_noopfun(void) {}
+
+void app_memory_write(void)             /* See dummy_console.c */
+__attribute__(( weak, alias("__app_noopfun") ));
+
+void app_bsp_start(void)
+__attribute__(( weak, alias("__app_noopfun") ));
+
+void app_bsp_pretasking_hook(void)
+__attribute__(( weak, alias("__app_noopfun") ));
+
+void app_bsp_predriver_hook(void)
+__attribute__(( weak, alias("__app_noopfun") ));
+
+
+LINKER_SYMBOL(__bsp_ram_start);
+LINKER_SYMBOL(__bsp_ram_end);
+LINKER_SYMBOL(WorkAreaBase);
+LINKER_SYMBOL(MsgAreaBase);
+LINKER_SYMBOL(MsgAreaSize);
+
+static char* bspMsgBuffer = (char*)MsgAreaBase;
+
+static void __bsp_outchar_to_memory(char c)
+{
+  static char* msgBuffer = (char*)MsgAreaBase;
+  *msgBuffer++ = c;
+  if (msgBuffer >= &bspMsgBuffer[(int)MsgAreaSize])  msgBuffer = bspMsgBuffer;
+  *msgBuffer   = 0x00;                /* Overwrite next location to show EOM */
+}
+
+
+void BSP_ask_for_reset(void)
+{
+  printk("\nSystem stopped, press RESET");
+  for(;;);
+  /*__asm__ __volatile ("sc");*/
+}
+
+
+void BSP_panic(char *s)
+{
+  printk("\n%s PANIC %s\n", _RTEMS_version, s);
+  BSP_ask_for_reset();
+}
+
+
+void _BSP_Fatal_error(unsigned int v)
+{
+  printk("\n%s FATAL ERROR %x\n", _RTEMS_version, v);
+  BSP_ask_for_reset();
+}
+
+
+/*===================================================================*/
+
+/*
+ *  BSP start routine.  Called by boot_card().
+ *
+ *  This routine does the bulk of the system initialization.
+ */
+void bsp_start(void)
+{
+  rtems_status_code  sc = RTEMS_SUCCESSFUL;
+  uintptr_t          intrStackStart;
+  uintptr_t          intrStackSize;
+  ppc_cpu_id_t       myCpu;
+  ppc_cpu_revision_t myCpuRevision;
+
+  /* Set the character output function;  The application may override this */
+  BSP_output_char = __bsp_outchar_to_memory;
+
+  /*
+   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
+   * function stores the result in global variables
+   * so that it can be used later...
+   */
+  myCpu         = get_ppc_cpu_type();
+  myCpuRevision = get_ppc_cpu_revision();
+  printk("CPU: 0x%04x,  Revision: 0x%04x = %d,  Name: %s\n",
+         myCpu, myCpuRevision, myCpuRevision, get_ppc_cpu_type_name(myCpu));
+
+  /*
+   *  Initialize the device driver parameters
+   */
+
+  /* Timebase register ticks/microsecond;  The application may override these */
+  bsp_clicks_per_usec        = 450;
+  bsp_timer_internal_clock   = true;
+  bsp_timer_average_overhead = 2;
+  bsp_timer_least_valid      = 3;
+
+  /*
+   * Initialize the interrupt related settings.
+   */
+  intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
+  intrStackSize  = rtems_configuration_get_interrupt_stack_size();
+
+  /*
+   * Initialize default raw exception handlers.
+   */
+  sc = ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+                          intrStackStart,
+                          intrStackSize);
+  if (sc != RTEMS_SUCCESSFUL)  BSP_panic("Cannot initialize exceptions");
+
+  /* Continue with application-specific initialization */
+  app_bsp_start();
+}
+
+
+/*
+ *  BSP pretasking hook.  Called just before drivers are initialized.
+ *  Used to setup libc and install any BSP extensions.
+ *
+ *  Must not use libc (to do io) from here, since drivers are not yet
+ *  initialized.
+ */
+
+void bsp_pretasking_hook(void)
+{
+  app_bsp_pretasking_hook();
+}
+
+
+/*
+ *  BSP predriver hook.  Called by boot_card() just before drivers are
+ *  initialized.  Clear out any stale interrupts here.
+ */
+void bsp_predriver_hook(void)
+{
+  app_bsp_predriver_hook();
+}

new file c/src/lib/libbsp/powerpc/virtex5/startup/dummy_console.c

@@ +1 @@
+#include <rtems.h>
+#include <rtems/libio.h>
+
+extern int app_memory_write(int minor, const char* buf, int len);
+
+static rtems_termios_callbacks gMemCallbacks = {
+        0,                /* firstOpen */
+        0,                /* lastClose */
+        0,                /* PollRead */
+        app_memory_write, /* write */
+        0,                /* SetAttr */
+        0,                /* stopRemoteTx */
+        0,                /* startRemoteTx */
+        0                 /* outputUsesInterrupts */
+};
+
+rtems_device_driver console_initialize(rtems_device_major_number major,
+                                       rtems_device_minor_number minor,
+                                       void*                     arg)
+{
+  rtems_status_code status;
+
+  rtems_termios_initialize();
+
+  status = rtems_io_register_name("/dev/console", major, 0);
+
+  if (status != RTEMS_SUCCESSFUL)  rtems_fatal_error_occurred (status);
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_device_driver console_open(rtems_device_major_number major,
+                                 rtems_device_minor_number minor,
+                                 void*                     arg)
+{
+  rtems_status_code sc;
+
+  sc = rtems_termios_open (major, minor, arg, &gMemCallbacks);
+
+  return sc;
+}
+
+rtems_device_driver console_close(rtems_device_major_number major,
+                                  rtems_device_minor_number minor,
+                                  void*                     arg)
+{
+  return rtems_termios_close(arg);
+}
+
+rtems_device_driver console_read(rtems_device_major_number major,
+                                 rtems_device_minor_number minor,
+                                 void*                     arg)
+{
+  return rtems_termios_read(arg);
+}
+
+rtems_device_driver console_write(rtems_device_major_number major,
+                                  rtems_device_minor_number minor,
+                                  void*                     arg)
+{
+  return rtems_termios_write(arg);
+}
+
+rtems_device_driver console_control(rtems_device_major_number major,
+                                    rtems_device_minor_number minor,
+                                    void*                     arg)
+{
+  return rtems_termios_ioctl(arg);
+}

new file c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds

@@ +1 @@
+/*
+ *  This file contains directives for the GNU linker which are specific to the
+ *  Virtex 5 PPC 440.  No assumptions are made on the firmware in the FPGA.
+ *  This file is intended to be used together with start.S to generate
+ *  downloadable code.
+ */
+
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
+OUTPUT_ARCH(powerpc)
+
+ENTRY(download_entry)
+
+MsgAreaSize       = DEFINED(MsgAreaSize)   ? MsgAreaSize   : 1K;
+RamBase           = DEFINED(RamBase)       ? RamBase       : 0x0;
+RamSize           = DEFINED(RamSize)       ? RamSize       : 4096M - MsgAreaSize;
+IntrStackSize     = DEFINED(IntrStackSize) ? IntrStackSize : 16K;
+StackSize         = DEFINED(StackSize)     ? StackSize     : 64K;
+HeapSize          = DEFINED(HeapSize)      ? HeapSize      : 0; /* 0=Use def */
+
+
+MEMORY
+{
+  VECTORS         : ORIGIN = 0x00000000, LENGTH = 8K
+  RAM             : ORIGIN = 0x00002000, LENGTH = 4096M - 8K
+}
+
+
+SECTIONS
+{
+  __exeentry      = download_entry;
+  __exestart      = 0x100;
+  .vectors __exestart : { *(.vectors)                           } > VECTORS
+
+  /* Read-only sections, merged into text segment: */
+  .interp         : { *(.interp)                                } > RAM
+  .hash           : { *(.hash)                                  } > RAM
+  .dynsym         : { *(.dynsym)                                } > RAM
+  .dynstr         : { *(.dynstr)                                } > RAM
+  .gnu.version    : { *(.gnu.version)                           } > RAM
+  .gnu.version_d  : { *(.gnu.version_d)                         } > RAM
+  .gnu.version_r  : { *(.gnu.version_r)                         } > RAM
+  .rela.text      : { *(.rela.text) *(.rela.gnu.linkonce.t*)    } > RAM
+  .rela.data      : { *(.rela.data) *(.rela.gnu.linkonce.d*)    } > RAM
+  .rela.rodata    : { *(.rela.rodata*) *(.rela.gnu.linkonce.r*) } > RAM
+  .rela.got       : { *(.rela.got)                              } > RAM
+  .rela.got1      : { *(.rela.got1)                             } > RAM
+  .rela.got2      : { *(.rela.got2)                             } > RAM
+  .rela.ctors     : { *(.rela.ctors)                            } > RAM
+  .rela.dtors     : { *(.rela.dtors)                            } > RAM
+  .rela.init      : { *(.rela.init)                             } > RAM
+  .rela.fini      : { *(.rela.fini)                             } > RAM
+  .rela.bss       : { *(.rela.bss)                              } > RAM
+  .rela.plt       : { *(.rela.plt)                              } > RAM
+  .rela.sdata     : { *(.rela.sdata)                            } > RAM
+  .rela.sbss      : { *(.rela.sbss)                             } > RAM
+  .rela.sdata2    : { *(.rela.sdata2)                           } > RAM
+  .rela.sbss2     : { *(.rela.sbss2)                            } > RAM
+  .rela.dyn       : { *(.rela.dyn)                              } > RAM
+
+  /* Initialization code */
+  .init           : { PROVIDE (_init = .);
+                      *ecrti.o(.init)
+                      KEEP(*(.init))
+                      *ecrtn.o(.init)
+                    } > RAM
+
+  .text           : { *(.entry)
+                      *(.text)
+                      *(.text.*)
+
+                      /* Special FreeBSD sysctl sections */
+                      . = ALIGN (16);
+                      __start_set_sysctl_set = .;
+                      *(set_sysctl_*);
+                      __stop_set_sysctl_set = ABSOLUTE(.);
+                      *(set_domain_*);
+                      *(set_pseudo_*);
+
+                      /* .gnu.warning sections are handled specially by elf32.em
+                       */
+                      *(.gnu.warning)
+                      *(.gnu.linkonce.t*)
+                    } > RAM
+
+  /* Finalization code */
+  .fini           : { PROVIDE (_fini = .);
+                      *ecrti.o(.fini)
+                      KEEP(*(.fini))
+                      *ecrtn.o(.fini)
+                    } > RAM
+
+  /* Miscellaneous read-only data */
+  .rodata         : { *(.rodata.* .gnu.linkonce.r*)                    } > RAM
+  .rodata1        : { *(.rodata1)                                      } > RAM
+
+  /* Initialised small data addressed as offsets from r2 */
+_SDA2_BASE_ = __SDATA2_START__ + 0x8000;
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)          } > RAM
+
+  /* Zeroed small data addressed as offsets from r2 */
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+
+                      /* Avoid empty sdata2/sbss2 area: __eabi would not set up
+                       * r2 which may be important if run-time loading is used
+                       */
+                      . += 1;
+
+                      PROVIDE (__SBSS2_END__ = .);
+                    } > RAM
+
+  /* Exception frame info */
+  .eh_frame       : { *(.eh_frame .eh_frame.*)                         } > RAM
+  .eh_frame_hdr   : { *(.eh_frame_hdr)                                 } > RAM
+
+  /*  Declares where the .text section ends */
+  _etext          = .;
+  PROVIDE (etext  = .);
+
+  /* Initialized R/W Data section goes in RAM */
+  .data           : { PROVIDE(__DATA_START__ = ABSOLUTE(.) );
+                      *(.data)
+                      *(.data.*)
+                      *(.gnu.linkonce.d*)
+                    } > RAM
+
+  .data1          : { *(.data1)                                        } > RAM
+
+                        PROVIDE (__EXCEPT_START__ = .);
+  .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*)       } > RAM
+                        PROVIDE (__EXCEPT_END__ = .);
+
+  .got1           : { *(.got1)                                         } > RAM
+
+  /* Put .ctors and .dtors next to the .got2 section, so that the pointers
+   * get relocated with -mrelocatable. Also put in the .fixup pointers.
+   * The current compiler no longer needs this, but keep it around for 2.7.2.
+   */
+                      PROVIDE (_GOT2_START_ = .);
+  .got2           : { *(.got2)                                         } > RAM
+
+  .dynamic        : { *(.dynamic)                                      } > RAM
+
+  .ctors          : { /* gcc uses crtbegin.o to find the start of
+                       * the constructors, so we make sure it is
+                       * first.  Because this is a wildcard, it
+                       * doesn't matter if the user does not
+                       * actually link against crtbegin.o; the
+                       * linker won't look for a file to match a
+                       * wildcard.  The wildcard also means that it
+                       * doesn't matter which directory crtbegin.o
+                       * is in.
+                       */
+                      KEEP (*crtbegin.o(.ctors))
+                      /* We don't want to include the .ctor section from
+                       * the crtend.o file until after the sorted ctors.
+                       * The .ctor section from the crtend file contains the
+                       * end of ctors marker and it must be last.
+                       */
+                      KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+                      KEEP (*(SORT(.ctors.*)))
+                      KEEP (*(.ctors))
+                    } > RAM
+
+  .dtors          : { KEEP (*crtbegin.o(.dtors))
+                      KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+                      KEEP (*(SORT(.dtors.*)))
+                      KEEP (*(.dtors))
+                    } > RAM
+
+                      PROVIDE (_FIXUP_START_ = .);
+  .fixup          : { *(.fixup)                                        } > RAM
+                      PROVIDE (_FIXUP_END_ = .);
+
+                      PROVIDE (_GOT2_END_ = .);
+
+                      PROVIDE (_GOT_START_ = .);
+  .got            : { __got_start = .;
+                      *(.got)
+                    } > RAM
+
+  .got.plt        : { *(.got.plt)                                      } > RAM
+                      PROVIDE (_GOT_END_ = .);
+
+  .jcr            : { KEEP (*(.jcr))                                   } > RAM
+
+  /* We want the small data sections together, so single-instruction offsets
+   * can access them all, and initialized data all before uninitialized, so
+   * we can shorten the on-disk segment size.
+   */
+  /* Initialised small data addressed as offsets from r13 */
+_SDA_BASE_ = __SDATA_START__ + 0x8000;
+  .sdata          : { *(.sdata* .gnu.linkonce.s.*)                     } > RAM
+
+  _edata          = .;
+  PROVIDE (edata  = .);
+
+  /* Zeroed small data addressed as offsets from r13 */
+  .sbss           : { PROVIDE (__sbss_start = .);
+                      *(.dynsbss)
+                      *(.sbss*)
+                      *(.gnu.linkonce.sb.*)
+                      *(.scommon)
+
+                      /* Avoid empty sdata/sbss area: __eabi would not set up
+                       * r13, which may be important if run-time loading is used
+                       */
+                      . += 1;
+
+                      PROVIDE (__SBSS_END__ = .);
+                      PROVIDE (__sbss_end   = .);
+                    } > RAM
+
+  .plt            : { *(.plt)                                          } > RAM
+  .iplt           : { *(.iplt)                                         } > RAM
+
+  /* Zeroed large data */
+  .bss            : { PROVIDE (__bss_start = .);
+                      *(.dynbss)
+                      *(.bss)
+                      *(.bss.*)
+                      *(.gnu.linkonce.b*)
+                      *(COMMON)
+
+                      PROVIDE (__bss_end = ALIGN(4));
+                      __bss_size = __bss_end - __bss_start;
+                    } > RAM
+
+  __exeend        = ALIGN(4);
+  __rtems_end     = .;
+  .               = ALIGN(0x20);        /* Align to a cache-line boundary */
+  PROVIDE(__bsp_ram_start = .);
+
+  /* Interrupt stack: aligned on a cache-line boundary */
+  .              += IntrStackSize;
+  __intrStack     = .;
+
+  /* Main stack lives here */
+  _stack          = ALIGN(0x20);        /* Align to a cache-line boundary */
+  .              += StackSize;
+  __stack_base    = .;                  /* Initial stack builds downwards */
+
+  /* RTEMS workspace: size specified by application */
+  WorkAreaBase    = ALIGN(0x20);        /* Align to a cache-line boundary */
+
+  /* The heap comes after the work space */
+
+   .              = RamBase + RamSize - MsgAreaSize;
+  PROVIDE(__bsp_ram_end = .);
+
+  /* Message area for capturing early printk output */
+  /* Placed here to be easily findable with a debugger */
+  MsgAreaBase     = __bsp_ram_end;
+  .              += MsgAreaSize;
+
+  __phy_ram_end   = .;                  /* True end of physical memory */
+
+  /DISCARD/ :
+  {
+    *(.comment)
+  }
+
+  /* Some configuration constants */
+  __vectors       = 0;
+}

new file c/src/lib/libbsp/powerpc/virtex5/startup/start.S

@@ +1 @@
+/*!@file      start.S
+*
+*  @brief     Initialization code to set up the CPU and call boot_card()
+*
+*  This "BSP" targets the Xilinx Virtex XC5VFX70T and related parts.  This
+*  BSP makes no assumptions on what firmware is loaded into the FPGA.
+*
+*  Provides the .entry section code.  This is the first code to run in
+*  the PPC after download to RAM.  Excecution in this case starts at
+*  'download_entry'.
+*
+*  The entrypoint 'start' is provided for the case where a bootloader has
+*  initialized the CPU, and all that remains to do is to set up a C
+*  environment and call boot_card.
+*
+*  Derived from virtex dlentry and others.
+*
+*  Some portions of this code follow section 3.4 of the PPC440x5 CPU Core User's
+*  Manual v7.1 from IBM.  Other parts were derived from examples provided
+*  by Xilinx in their ML510 Reference Designs, e.g., ml510_bsb1_design_ppc440.
+*  See boot.S in standalone/, for example.
+*
+*  References:
+*      Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG200 (v1.8)
+*      http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
+*
+*      PowerPC 440x5 Embedded Processor Core User's Manual (Version 7.1)
+*      https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_440_Embedded_Core
+*
+*  @author    Richard Claus <claus@SLAC.Stanford.edu>
+*
+*  @date      March 4, 2011 -- Created
+*
+*  $Revision: 675 $
+*
+*  @verbatim                    Copyright 2011
+*                                      by
+*                         The Board of Trustees of the
+*                       Leland Stanford Junior University.
+*                              All rights reserved.
+*
+*         Work supported by the U.S. Department of Energy under contract
+*       DE-AC03-76SF00515.
+*
+*                               Disclaimer Notice
+*
+*        The items furnished herewith were developed under the sponsorship
+*   of the U.S. Government.  Neither the U.S., nor the U.S. D.O.E., nor the
+*   Leland Stanford Junior University, nor their employees, makes any war-
+*   ranty, express or implied, or assumes any liability or responsibility
+*   for accuracy, completeness or usefulness of any information, apparatus,
+*   product or process disclosed, or represents that its use will not in-
+*   fringe privately-owned rights.  Mention of any product, its manufactur-
+*   er, or suppliers shall not, nor is it intended to, imply approval, dis-
+*   approval, or fitness for any particular use.  The U.S. and the Univer-
+*   sity at all times retain the right to use and disseminate the furnished
+*   items for any purpose whatsoever.                       Notice 91 02 01
+*
+*  @endverbatim
+*/
+
+#include <rtems/asm.h>
+#include <rtems/powerpc/powerpc.h>
+
+#define   V_TS_SZ_I    0x0290      // V,TS=0(Inst),SIZE=9,TID=0
+#define   V_TS_SZ_D    0x0390      // V,TS=1(Data),SIZE=9,TID=0
+#define   WIMG_U_S_0   0x043F      // !(U0-3),!W, I,!M,!G,!E,UX,UW,UR,SX,SW,SR
+#define   WIMG_U_S_1   0x003F      // !(U0-3),!W,!I,!M,!G,!E,UX,UW,UR,SX,SW,SR
+#define   PAGE_SZ      0x10000000  // 256 MB
+
+/*
+ *  The virtex ELF link scripts support some special sections:
+ *    .entry    The actual entry point
+ *    .vectors  The section containing the interrupt entry veneers.
+ */
+
+/*
+ *  Downloaded code loads the vectors separately to 0x00000100,
+ *  so .entry can be over 256 bytes.
+ *
+ *  The other sections are linked in the following order:
+ *    .entry
+ *    .text
+ *    .data
+ *    .bss
+ *  see linker command file for section placement
+ *
+ *  The initial stack is set to __stack_base
+ *
+ *  All the entry veneer has to do is to clear the BSS.
+ */
+
+        .section .entry
+
+        PUBLIC_VAR(download_entry)
+        PUBLIC_VAR(__rtems_entry_point)
+SYM(download_entry):
+SYM(__rtems_entry_point):
+        b       startupDL         /* Entry point used by xmd dow command */
+
+        PUBLIC_VAR (start)
+SYM(start):
+        b       startupBL         /* Entry point used by bootLoader */
+
+base_addr:
+       /*-------------------------------------------------------------------
+        * Parameters from linker
+        *-----------------------------------------------------------------*/
+toc_pointer:
+        .long   __got_start
+bss_length:
+        .long   __bss_size
+bss_addr:
+        .long   __bss_start
+stack_top:
+        .long   __stack_base
+
+
+        .eject
+
+       /*------------------------------------------------------------------
+        * This code follows section 3.4 of the PPC440x5 CPU Core User's
+        * Manual.  The numbers in the comments refer to the step numbers
+        * therein.  Some of the implementation comes from examples provided
+        * by Xilinx in their ML510 Reference Designs, e.g.,
+        * ml510_bsb1_design_ppc440.  See boot.S in standalone/.
+        *------------------------------------------------------------------*/
+       /*------------------------------------------------------------------
+        * This code is designed to accomodate warm restarts, in which the
+        * application software triggers the restart of the system by branching
+        * to the following code (either boot or boot1) without causing
+        * one of the hardware resets: core, chip, system or JTAG (section
+        * 3.2,3 in the Power PC 440-S Embedded Processor Core User's Manual).
+        *-----------------------------------------------------------------*/
+
+       /* -----------------------------------------------------------------
+        * Setup CPU
+        *-----------------------------------------------------------------*/
+first:  li      r0,0              // Clear r0
+
+       /* -----------------------------------------------------------------
+        * Initialize the memory system.
+        *------------------------------------------------------------------*/
+        iccci   r0,r0             // 2. Invalidate instruction cache
+        dccci   r0,r0             // 3. Invalidate data cache
+        msync                     // 4. Force in-progress data PLB ops to complete
+
+        mfdbcr0 r2                // 5. Disable all debug events
+        lis     r3,0x8100
+        and     r2,r2,r3          // Ignore EDM,TRAP to allow XMD use
+        mtdbcr0 r2
+        li      r2,-1
+        mtdbsr  r2                // 6. Initialize all debug event status
+
+       /*------------------------------------------------------------------
+        * Set Core Configuration Register 0 as follows:
+        * sum: 0x00200000
+        * bit  1    off  Parity Recovery Enable
+        * bit  4    off  Cache Read Parity Enable
+        * bit 10    on   Disable Store Gathering
+        * bit 11    off  Disable APU Instruction Broadcast
+        * bit 16    off  Disable Trace Broadcast
+        * bit 17:18 off  Specifies behaviour of icbt,dcbt/dcbtst insts
+        * bit 23    off  Force Load/Store Alignment
+        * bit 28:29 off  Instruction Cache Speculative Line Count
+        * bit 30:31 off  Instruction Cache Speculative Line Threshold
+        *            NB: UG200/pg 21: Spec. prefetching must be disabled
+        *------------------------------------------------------------------*/
+
+        lis     r2,0x0020         // 7. Set CCR0: DSTG
+        mtccr0  r2                // Configure CCR0
+
+        mtspr   ccr1,r0           // 8. Clear CCR1
+
+       /*------------------------------------------------------------------
+        * 9. Configure cache regions
+        *------------------------------------------------------------------*/
+        mtspr   inv0,r0
+        mtspr   inv1,r0
+        mtspr   inv2,r0
+        mtspr   inv3,r0
+        mtspr   dnv0,r0
+        mtspr   dnv1,r0
+        mtspr   dnv2,r0
+        mtspr   dnv3,r0
+        mtspr   itv0,r0
+        mtspr   itv1,r0
+        mtspr   itv2,r0
+        mtspr   itv3,r0
+        mtspr   dtv0,r0
+        mtspr   dtv1,r0
+        mtspr   dtv2,r0
+        mtspr   dtv3,r0
+
+       /*------------------------------------------------------------------
+        * Cache victim limits
+        * floors 0, ceiling max to use the entire cache -- nothing locked
+        *------------------------------------------------------------------*/
+        lis     r2,   0x0001f800@h
+        ori     r2,r2,0x0001f800@l
+        mtspr   ivlim,r2
+        mtspr   dvlim,r2
+
+       /*------------------------------------------------------------------
+        * Configure instruction and data cache regions:
+        * Set up register constants (r6,r7), page index (r5), address
+        * variable (r4), EPN_V_TS bits (r3)
+        *
+        * Word 0 bits:  0xX0000290, 0xX0000390
+        * Bits  Field  Inst  Data  Description
+        *  0:21  EPN   0-15  0-15  Effective Page Number
+        *    22  V     1     1     Valid
+        *    23  TS    0     1     Translation Address Space
+        * 24:27  SIZE  9     9     Page Size (9 = 256 MB)
+        * 38:31  TPAR  0     0     Tag Parity
+        * 32:39  TID   0     0     Translation ID (in the MMUCR)
+        *
+        * Word 1 bits:  0x00000000, 0x00000000
+        * Bits  Field  Inst  Data  Description
+        *  0:21  RPN   0     0     Real Page Number
+        * 22:23  PAR1  0     0     Parity for TLB word 1
+        * 28:31  ERPN  0     0     Extended Real Page Number
+        *
+        * Word 2 bits:  0x0000043f, 0x00000c3f
+        * Bits  Field  Inst  Data  Description
+        *  0: 1  PAR2  0     0     Parity for TLB word 2
+        *    16  U0    0     0     User-Defineable Storage Attribute 0
+        *    17  U1    0     0     User-Defineable Storage Attribute 1
+        *    18  U2    0     0     User-Defineable Storage Attribute 2
+        *    19  U3    0     0     User-Defineable Storage Attribute 3
+        *    20  W     0     0     Write-Through
+        *    21  I     1     1     Caching Inhibited
+        *    22  M     0     0     Memory Coherence Required
+        *    23  G     0     0     Guarded
+        *    24  E     0     0     Endian
+        *    26  UX    1     1     User State Execute Enable
+        *    27  UW    1     1     User State Write Enable
+        *    28  UR    1     1     User State Read Enable
+        *    29  SX    1     1     Supervisor State Execute Enable
+        *    30  SW    1     1     Supervisor State Write Enable
+        *    31  SR    1     1     Supervisor State Read Enable
+        *------------------------------------------------------------------*/
+
+        mtspr   mmucr,r0          // 10a. Clear MMUCR
+        li      r7,WIMG_U_S_1     // Word 2: Pages are NOT cache inhibited
+        lis     r6,   PAGE_SZ@h   // Page size constant
+        ori     r6,r6,PAGE_SZ@l
+        mr      r5,r0             // TLB entry index
+        mr      r4,r0             // Initialize RPN to zero
+        mflr    r28               // Save return address
+        bl      tlbSetup          // 10b. Set up the TLBs
+        mtlr    r28               // Restore return address
+
+       /*------------------------------------------------------------------
+        * Select whether Wait Enable, interrupts/exceptions and which address
+        * spaces should be enabled when application starts
+        *------------------------------------------------------------------*/
+        lis     r0,   0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0
+        ori     r0,r0,0x00000000@l
+        mtsrr1  r0
+        mtsrr0  r28               // Return address
+        rfi                       // Context synchronize to invalidate shadow TLB contents
+
+
+       /*-------------------------------------------------------------------
+        * Entry point used when downloaded, e.g. through XMD
+        *------------------------------------------------------------------*/
+startupDL:
+       /*-------------------------------------------------------------------
+        * Do initialization up to the point where a context sync is required
+        *------------------------------------------------------------------*/
+        bl      first             // Do first things first
+
+       /*-------------------------------------------------------------------
+        * 11. Tell the processor where the exception vector table will be
+        *------------------------------------------------------------------*/
+        .extern SYM(__vectors)
+        lis     r2, __vectors@h     /* set EVPR exc. vector prefix */
+        mtspr   ivpr,r2
+
+       /*------------------------------------------------------------------
+        * Set up default exception and interrupt vectors
+        *------------------------------------------------------------------*/
+        li       r1,0x100
+        mtivor0  r1
+        addi     r1,r1,0x100
+        mtivor1  r1
+        addi     r1,r1,0x100
+        mtivor2  r1
+        addi     r1,r1,0x100
+        mtivor3  r1
+        addi     r1,r1,0x100
+        mtivor4  r1
+        addi     r1,r1,0x100
+        mtivor5  r1
+        addi     r1,r1,0x100
+        mtivor6  r1
+        addi     r1,r1,0x100
+        mtivor7  r1
+        addi     r1,r1,0x100
+        mtivor8  r1
+        addi     r1,r1,0x100
+        mtivor9  r1
+        addi     r1,r1,0x100
+        mtivor10 r1
+        addi     r1,r1,0x100
+        mtivor11 r1
+        addi     r1,r1,0x100
+        mtivor12 r1
+        addi     r1,r1,0x100
+        mtivor13 r1
+        addi     r1,r1,0x100
+        mtivor14 r1
+        addi     r1,r1,0x100
+        mtivor15 r1
+
+       /*------------------------------------------------------------------
+        * 12. Configure debug facilities
+        *------------------------------------------------------------------*/
+        mtdbcr1 r0
+        mtdbcr2 r0
+        mtiac1  r0
+        mtiac2  r0
+        mtiac3  r0
+        mtiac4  r0
+        mtdac1  r0
+        mtdac2  r0
+        mtdvc1  r0
+        mtdvc2  r0
+        mfdbcr0 r2                // Freeze timers on debug events
+        ori     r2,r2,0x0001
+        mtdbcr0 r2
+        isync
+
+       /*-------------------------------------------------------------------
+        * 13. Configure timer facilities
+        *------------------------------------------------------------------*/
+        mtdec   r0                // Clear Decrementer to prevent exception
+        mttbu   r0                // Clear Timebase to prevent Fixed Interval..
+        mttbl   r0                // ..timer and Watchdog Timer exceptions
+        mtpit   r0                // Programmable interval timer
+        li      r1,-1             // -1 to clear TSR
+        mttsr   r1                // Timer status register
+
+       /*-------------------------------------------------------------------
+        * Clear out stale values in certain registers to avoid confusion
+        *------------------------------------------------------------------*/
+        li      r0,0
+        mtcrf   0xff,r0           // Need for simulation
+        mtctr   r0                // Counter register
+        mtxer   r0                // Fixed-point exception register
+        mtesr   r0                // Exception syndrome register
+        mtdear  r0                // Data exception address register
+        mtmcsr  r0                // Machine check syndrome register
+
+       /* Fall through */
+
+       /* -------------------------------------------------------------------
+        * If a bootloader has run that has already initialized the CPU,
+        * which among other things has loaded this code into memory and
+        * jumped to start above, the initialization above does not need
+        * to be redone.  Execution thus resumes here.
+        *------------------------------------------------------------------*/
+
+startupBL:
+       /*-------------------------------------------------------------------
+        * Load the parameter table base address
+        *------------------------------------------------------------------*/
+        lis     r1,   base_addr@h
+        ori     r1,r1,base_addr@l
+
+       /*-------------------------------------------------------------------
+        * Setup stack for RTEMS and call boot_card(). From this
+        * point forward registers will be used in accordance with the
+        * PowerPC EABI.
+        *
+        * boot_card() supervises the initialization of RTEMS and the C
+        * library.  It calls bsp_start(), bsp_pretasking_hook(), etc.
+        *------------------------------------------------------------------*/
+        lwz     r2,toc_pointer-base_addr(r1)        /* set r2 to toc */
+        lwz     r1,stack_top-base_addr(r1)          /* set r1 to stack_top */
+
+        /* Align as required by ABI */
+        li      r3,PPC_STACK_ALIGNMENT-1
+        andc    r1,r1,r3
+
+       /*-------------------------------------------------------------------
+        * Set up r2 and r13. Upon entry r1 must have a nonzero value
+        *  as it will be stored in an "init done" flag. Stupid but true.
+        *  r1 must also be set up as a stack pointer as __eabi() jumps
+        *  to __init() which has a standard function prolog.
+        *------------------------------------------------------------------*/
+        bl      __eabi              /* setup EABI and SYSV environment */
+
+       /*-------------------------------------------------------------------
+        * Zero the .bss, .sbss and .sbss2 sections.
+        * Must have r2 and r13 properly set.
+        *------------------------------------------------------------------*/
+        bl      zero_bss            /* Assume Bank regs set up..., cache etc. */
+
+       /*-------------------------------------------------------------------
+        * Create a minimal stack frame for this code, the caller of boot_card().
+        *------------------------------------------------------------------*/
+        addi    r1,r1,-PPC_MINIMUM_STACK_FRAME_SIZE
+
+        xor     r3,r3,r3            /* Clear r3 */
+        stw     r3,0(r1)            /* Clear stack chain */
+        stw     r3,4(r1)
+        stw     r3,8(r1)
+        stw     r3,12(r1)
+        lis     r5,environ@ha
+        la      r5,environ@l(r5)    /* environp */
+
+       /*-------------------------------------------------------------------
+        * Call boot_card() with its arguments, the command-line pointer and
+        * the argument count, set to NULL.
+        *------------------------------------------------------------------*/
+        li      r4,0                /* argv */
+        li      r3,0                /* argc */
+        .extern SYM (boot_card)
+        b       SYM (boot_card)     /* call the first C routine */
+
+
+        .eject
+
+       /*------------------------------------------------------------------
+        * Set up TLB entries: 2 entries are needed for the same 256MB page
+        * one for instruction memory and the other for data memory.
+        * (TS bit=0 for instructions)
+        *------------------------------------------------------------------*/
+tlbSetup:
+1:      ori     r3,r4,V_TS_SZ_I   // Fold V_TS_SZ in with EPN=RPN
+        tlbwe   r3,r5,0           // Word 0: EPN_V_TS_SZ (Instructions)
+        tlbwe   r4,r5,1           // Word 1: RPN_ERPN
+        tlbwe   r7,r5,2           // Word 2: WIMG_U_S
+        ori     r3,r4,V_TS_SZ_D   // Fold V_TS_SZ in with EPN=RPN
+        addi    r5,r5,1           // Next TLB entry
+        tlbwe   r3,r5,0           // Word 0: EPN_V_TS_SZ (Data)
+        tlbwe   r4,r5,1           // Word 1: RPN_ERPN
+        tlbwe   r7,r5,2           // Word 2: WIMG_U_S
+        add     r4,r4,r6          // Increment RPN to next 256MB block
+        addi    r5,r5,1           // Next TLB entry
+        cmpwi   r5,32             // Done yet?
+        bne     1b
+        li      r0,0
+2:                                // Zero out index 32-63 TLB entries
+        tlbwe   r0,r5,0
+        tlbwe   r0,r5,1
+        tlbwe   r0,r5,2
+        addi    r5,r5,1
+        cmpwi   r5,64
+        bne     2b
+
+        blr