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1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsARMCycV |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Dornierstr. 4 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <info@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H |
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22 | #define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H |
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23 | |
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24 | /** |
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25 | * @defgroup RTEMSBSPsARMCycV Intel Cyclone V |
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26 | * |
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27 | * @ingroup RTEMSBSPsARM |
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28 | * |
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29 | * @brief Intel Cyclone V Board Support Package. |
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30 | * |
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31 | * @{ |
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32 | */ |
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33 | |
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34 | #include <bspopts.h> |
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35 | |
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36 | #define BSP_FEATURE_IRQ_EXTENSION |
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37 | |
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38 | #ifndef ASM |
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39 | |
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40 | #include <rtems.h> |
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41 | |
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42 | #include <bsp/default-initial-extension.h> |
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43 | |
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44 | #ifdef __cplusplus |
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45 | extern "C" { |
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46 | #endif /* __cplusplus */ |
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47 | |
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48 | #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 |
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49 | |
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50 | #define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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51 | |
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52 | #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) |
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53 | |
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54 | #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) |
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55 | |
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56 | #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) |
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57 | |
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58 | #ifndef BSP_ARM_A9MPCORE_PERIPHCLK |
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59 | extern uint32_t altera_cyclone_v_a9mpcore_periphclk; |
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60 | #define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk |
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61 | #define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK |
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62 | #endif |
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63 | |
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64 | #define BSP_ARM_L2C_310_BASE 0xfffef000 |
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65 | |
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66 | #define BSP_ARM_L2C_310_ID 0x410000c9 |
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67 | |
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68 | #ifdef __cplusplus |
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69 | } |
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70 | #endif /* __cplusplus */ |
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71 | |
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72 | #endif /* ASM */ |
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73 | |
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74 | /* @} */ |
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75 | |
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76 | #endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */ |
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