1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
---|
2 | |
---|
3 | /** |
---|
4 | * @file |
---|
5 | * |
---|
6 | * @ingroup RTEMSBSPsARMCycV |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG |
---|
11 | * |
---|
12 | * Redistribution and use in source and binary forms, with or without |
---|
13 | * modification, are permitted provided that the following conditions |
---|
14 | * are met: |
---|
15 | * 1. Redistributions of source code must retain the above copyright |
---|
16 | * notice, this list of conditions and the following disclaimer. |
---|
17 | * 2. Redistributions in binary form must reproduce the above copyright |
---|
18 | * notice, this list of conditions and the following disclaimer in the |
---|
19 | * documentation and/or other materials provided with the distribution. |
---|
20 | * |
---|
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
---|
22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
---|
23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
---|
24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
---|
25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
---|
26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
---|
27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
---|
28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
---|
29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
---|
30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
---|
31 | * POSSIBILITY OF SUCH DAMAGE. |
---|
32 | */ |
---|
33 | |
---|
34 | #ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H |
---|
35 | #define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H |
---|
36 | |
---|
37 | /** |
---|
38 | * @defgroup RTEMSBSPsARMCycV Intel Cyclone V |
---|
39 | * |
---|
40 | * @ingroup RTEMSBSPsARM |
---|
41 | * |
---|
42 | * @brief Intel Cyclone V Board Support Package. |
---|
43 | * |
---|
44 | * @{ |
---|
45 | */ |
---|
46 | |
---|
47 | #include <bspopts.h> |
---|
48 | |
---|
49 | #define BSP_FEATURE_IRQ_EXTENSION |
---|
50 | |
---|
51 | #ifndef ASM |
---|
52 | |
---|
53 | #include <rtems.h> |
---|
54 | |
---|
55 | #include <bsp/default-initial-extension.h> |
---|
56 | |
---|
57 | #ifdef __cplusplus |
---|
58 | extern "C" { |
---|
59 | #endif /* __cplusplus */ |
---|
60 | |
---|
61 | #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 |
---|
62 | |
---|
63 | #define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
---|
64 | |
---|
65 | #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) |
---|
66 | |
---|
67 | #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) |
---|
68 | |
---|
69 | #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) |
---|
70 | |
---|
71 | #ifndef BSP_ARM_A9MPCORE_PERIPHCLK |
---|
72 | extern uint32_t altera_cyclone_v_a9mpcore_periphclk; |
---|
73 | #define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk |
---|
74 | #define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK |
---|
75 | #endif |
---|
76 | |
---|
77 | #define BSP_ARM_L2C_310_BASE 0xfffef000 |
---|
78 | |
---|
79 | #define BSP_ARM_L2C_310_ID 0x410000c9 |
---|
80 | |
---|
81 | #ifdef __cplusplus |
---|
82 | } |
---|
83 | #endif /* __cplusplus */ |
---|
84 | |
---|
85 | #endif /* ASM */ |
---|
86 | |
---|
87 | /* @} */ |
---|
88 | |
---|
89 | #endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */ |
---|