| 11 | '''Goal of the project:''' The goal of this project is to allow a developer to utilize a full power from a HiFive1 processor by means of providing POSIX-compliant RTOS capabilities for Freedom E310 cores. |
| 12 | |
| 13 | '''Project Objectives''': At the of the project I want to have a working with capabilities of task switching and interrupt handling. Another objective is haveing working console and clock drivers. |
| 14 | |
| 15 | == Description and references == |
| 16 | |
| 17 | Hifive1 board is a small evaluation board with a SiFive Freedom E310-G000 SoC. Freedom E310-G000 SoC (FE310-G000) is built around the E31 Coreplex instantiated in the Freedom E300 platform. E31 Coreplex core implements RISC-V architecture. References: |
| 18 | |
| 19 | [https://www.sifive.com/documentation/boards/hifive1/hifive1-getting-started-guide/ HiFive1 Getting Started Guide] |
| 20 | |
| 21 | [https://www.sifive.com/documentation/chips/freedom-e310-g000-manual/ Freedom E310-G000 Manual] |
| 22 | |
| 23 | [https://www.sifive.com/documentation/freedom-soc/freedom-e300-platform-reference-manual/ Freedom E300 Platform Reference Manual] |
| 24 | |
| 25 | [https://www.sifive.com/documentation/coreplex/e31-coreplex-manual/ E31 Coreplex Manual] |
| 26 | |
| 27 | [https://riscv.org/specifications/ RISC-V architecture description] |
| 28 | |
| 29 | '''Note:''' at the time of the writing the current Privileged Mode draft is of version 1.10. But E31 Coreplex core implements PM v.1.8 or v.1.9. |