wiki:GSoC/2017/RTEMS_for_HiFive1

RTEMS BSP for HiFive1

Student: Obrezkov Denis.

Mentors: Joel Sherrill, Hesham Almatary.

Introduction: Blog.

Goal of the project: The goal of this project is to allow a developer to utilize a full power from a HiFive1 processor by means of providing POSIX-compliant RTOS capabilities for Freedom E310 cores.

Project Objectives: At the of the project I want to have a working with capabilities of task switching and interrupt handling. Another objective is haveing working console and clock drivers.

Board Overview

BSP Information
BSP_name HiFive1 (FE310-G000)
Manufacturer SiFive
Board_URL https://www.sifive.com/documentation/boards/hifive1/hifive1-overview/
Architecture RISC-V
Piveleged ISA 1.9
CPU_model SiFive Freedom E310 (FE310)
Simulator Yes (spike)
RAM 16 KB Instruction Cache, 16 KB Data Scratchpad
ROM 16 MB SPI Flash
Serial 2 x UARTs (1 available), 2 x SPI (+1 Flash)
Dimensions 68 mm x 51 mm
Other 19 Digital I/O pins

Description and references

Hifive1 board is a small evaluation board with a SiFive? Freedom E310-G000 SoC. Freedom E310-G000 SoC (FE310-G000) is built around the E31 Coreplex instantiated in the Freedom E300 platform. E31 Coreplex core implements RISC-V architecture. References:

HiFive1 Getting Started Guide

Freedom E310-G000 Manual

Freedom E300 Platform Reference Manual

E31 Coreplex Manual

RISC-V architecture description

Note: at the time of the writing the current Privileged Mode draft is of version 1.10. But E31 Coreplex core implements PM v.1.8 or v.1.9.

Last modified on Aug 16, 2017 at 12:00:23 AM Last modified on Aug 16, 2017, 12:00:23 AM