#4771 closed defect (fixed)

Versal UART issues

Reported by: Chris Johns Owned by: Chris Johns
Priority: normal Milestone: 6.1
Component: arch/aarch64 Version: 6
Severity: normal Keywords:
Cc: Blocked By:


The Versal polled mode it broken when building. The disable all interrupt call is not built in polled mode.

The UART interrupt mode behaves differently with a small stand alone app than a full app with libbsd. A full application with libbsd seems to behave while the small app exhibit the "not tx interrupt on FIFO load" issue.

Attachments (1)

0001-aarch64-versal-Fix-uart-interrupt-issues.patch (1.5 KB) - added by Aaron N on 12/05/22 at 22:28:42.

Download all attachments as: .zip

Change History (3)

comment:1 Changed on 02/09/23 at 02:27:13 by Chris Johns

The UART IP is based on the standard ARM IP however Xilinx have finally reported to me the interrupts are not the same as the ARM IP. There is weird issue around needing to prime the FIFO to half plus one to generate the first TX interrupt.

Xilinx has confirmed this will not change across the range of ACAP devices.

The main issue this raises is using the UART for a specialized protocol and not a terminal where sending a number of carriage returns is harmless.

comment:2 Changed on 05/17/23 at 04:23:43 by Aaron N

Resolution: fixed
Status: assignedclosed
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