Changeset d5ca821 in rtems


Ignore:
Timestamp:
Apr 7, 2015, 12:28:29 PM (5 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
8b29637c
Parents:
c1c37a1
git-author:
Daniel Hellstrom <daniel@…> (04/07/15 12:28:29)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:26)
Message:

LEON: converted AT697,GRPCi,GRPCI2,PCIF to BSD header

Location:
c/src/lib/libbsp/sparc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c

    rc1c37a1 rd5ca821  
    9797#define DBG(x...)
    9898#endif
    99 
    100 #define PCI_INVALID_VENDORDEVICEID      0xffffffff
    101 #define PCI_MULTI_FUNCTION              0x80
    10299
    103100struct at697pci_regs {
  • c/src/lib/libbsp/sparc/shared/pci/grpci.c

    rc1c37a1 rd5ca821  
    6969#define DBG(x...)
    7070#endif
    71 
    72 #define PCI_INVALID_VENDORDEVICEID      0xffffffff
    73 #define PCI_MULTI_FUNCTION              0x80
    7471
    7572/*
     
    439436        if ( !priv->bt_enabled && ((priv->regs->page0 & PAGE0_BTEN) == PAGE0_BTEN) ) {
    440437                /* Byte twisting is on, turn it off */
    441                 grpci_cfg_w32(host, PCI_BASE_ADDRESS_0, 0xffffffff);
    442                 grpci_cfg_r32(host, PCI_BASE_ADDRESS_0, &addr);
     438                grpci_cfg_w32(host, PCIR_BAR(0), 0xffffffff);
     439                grpci_cfg_r32(host, PCIR_BAR(0), &addr);
    443440                /* Setup bar0 to nonzero value */
    444                 grpci_cfg_w32(host, PCI_BASE_ADDRESS_0,
     441                grpci_cfg_w32(host, PCIR_BAR(0),
    445442                                CPU_swap_u32(0x80000000));
    446443                /* page0 is accessed through upper half of bar0 */
     
    455452
    456453        /* Get the GRPCI Host PCI ID */
    457         grpci_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
     454        grpci_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
    458455
    459456        /* set 1:1 mapping between AHB -> PCI memory */
     
    461458
    462459        /* determine size of target BAR1 */
    463         grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
    464         grpci_cfg_r32(host, PCI_BASE_ADDRESS_1, &addr);
     460        grpci_cfg_w32(host, PCIR_BAR(1), 0xffffffff);
     461        grpci_cfg_r32(host, PCIR_BAR(1), &addr);
    465462        priv->bar1_size = (~(addr & ~0xf)) + 1;
    466463
    467464        /* and map system RAM at pci address 0x40000000 */
    468465        priv->bar1_pci_adr &= ~(priv->bar1_size - 1); /* Fix alignment of BAR1 */
    469         grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, priv->bar1_pci_adr);
     466        grpci_cfg_w32(host, PCIR_BAR(1), priv->bar1_pci_adr);
    470467        priv->regs->page1 = priv->bar1_pci_adr;
    471468
     
    477474         * will set it according to the max size of the PCI FIFO.
    478475         */
    479         grpci_cfg_w8(host, PCI_CACHE_LINE_SIZE, 0xff);
    480         grpci_cfg_w8(host, PCI_LATENCY_TIMER, 0x40);
     476        grpci_cfg_w8(host, PCIR_CACHELNSZ, 0xff);
     477        grpci_cfg_w8(host, PCIR_LATTIMER, 0x40);
    481478
    482479        /* set as bus master and enable pci memory responses */ 
    483         grpci_cfg_r32(host, PCI_COMMAND, &data);
    484         data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    485         grpci_cfg_w32(host, PCI_COMMAND, data);
     480        grpci_cfg_r32(host, PCIR_COMMAND, &data);
     481        data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
     482        grpci_cfg_w32(host, PCIR_COMMAND, data);
    486483
    487484        /* unmask all PCI interrupts at PCI Core, not all GRPCI cores support
  • c/src/lib/libbsp/sparc/shared/pci/grpci2.c

    rc1c37a1 rd5ca821  
    8181#define DBG(x...)
    8282#endif
    83 
    84 #define PCI_INVALID_VENDORDEVICEID      0xffffffff
    85 #define PCI_MULTI_FUNCTION              0x80
    8683
    8784/*
     
    655652
    656653        /* Get the GRPCI2 Host PCI ID */
    657         grpci2_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
     654        grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
    658655
    659656        /* Get address to first (always defined) capability structure */
    660         grpci2_cfg_r8(host, PCI_CAP_PTR, &capptr);
     657        grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
    661658        if (capptr == 0)
    662659                return -1;
     
    680677                pciadr = barcfg[i].pciadr;
    681678                ahbadr = barcfg[i].ahbadr;
    682                 size |= PCI_BASE_ADDRESS_MEM_PREFETCH;
     679                size |= PCIM_BAR_MEM_PREFETCH;
    683680
    684681                grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
    685682                grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
    686                 grpci2_cfg_w32(host, PCI_BASE_ADDRESS_0+i*4, pciadr);
     683                grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
    687684        }
    688685
    689686        /* set as bus master and enable pci memory responses */ 
    690         grpci2_cfg_r32(host, PCI_COMMAND, &data);
    691         data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    692         grpci2_cfg_w32(host, PCI_COMMAND, data);
     687        grpci2_cfg_r32(host, PCIR_COMMAND, &data);
     688        data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
     689        grpci2_cfg_w32(host, PCIR_COMMAND, data);
    693690
    694691        /* Enable Error respone (CPU-TRAP) on illegal memory access */
  • c/src/lib/libbsp/sparc/shared/pci/pcif.c

    rc1c37a1 rd5ca821  
    364364
    365365        /* Get the PCIF Host PCI ID */
    366         pcif_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
     366        pcif_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
    367367
    368368        /* set 1:1 mapping between AHB -> PCI memory space, for all Master cores */
     
    384384
    385385        /* determine size of target BAR1 */
    386         pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
    387         pcif_cfg_r32(host, PCI_BASE_ADDRESS_1, &size);
     386        pcif_cfg_w32(host, PCIR_BAR(1), 0xffffffff);
     387        pcif_cfg_r32(host, PCIR_BAR(1), &size);
    388388        priv->bar1_size = (~(size & ~0xf)) + 1;
    389389
    390         pcif_cfg_w32(host, PCI_BASE_ADDRESS_0, 0);
    391         pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, SYSTEM_MAINMEM_START);
    392         pcif_cfg_w32(host, PCI_BASE_ADDRESS_2, 0);
    393         pcif_cfg_w32(host, PCI_BASE_ADDRESS_3, 0);
    394         pcif_cfg_w32(host, PCI_BASE_ADDRESS_4, 0);
    395         pcif_cfg_w32(host, PCI_BASE_ADDRESS_5, 0);
     390        pcif_cfg_w32(host, PCIR_BAR(0), 0);
     391        pcif_cfg_w32(host, PCIR_BAR(1), SYSTEM_MAINMEM_START);
     392        pcif_cfg_w32(host, PCIR_BAR(2), 0);
     393        pcif_cfg_w32(host, PCIR_BAR(3), 0);
     394        pcif_cfg_w32(host, PCIR_BAR(4), 0);
     395        pcif_cfg_w32(host, PCIR_BAR(5), 0);
    396396
    397397        /* set as bus master and enable pci memory responses */ 
    398         pcif_cfg_r32(host, PCI_COMMAND, &data);
    399         data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    400         pcif_cfg_w32(host, PCI_COMMAND, data);
     398        pcif_cfg_r32(host, PCIR_COMMAND, &data);
     399        data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
     400        pcif_cfg_w32(host, PCIR_COMMAND, data);
    401401
    402402        /* Successful */
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