Changeset 8b29637c in rtems


Ignore:
Timestamp:
Apr 7, 2015, 12:31:07 PM (5 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
9b292ea
Parents:
d5ca821
git-author:
Daniel Hellstrom <daniel@…> (04/07/15 12:31:07)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:27)
Message:

LEON: converted PCI peripherals to BSD header

Location:
c/src/lib/libbsp/sparc/shared/pci
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/pci/gr_701.c

    rd5ca821 r8b29637c  
    270270
    271271        /* Enable I/O and Mem accesses */
    272         pci_cfg_r32(pcidev, PCI_COMMAND, &com1);
    273         com1 |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
    274         pci_cfg_w32(pcidev, PCI_COMMAND, com1);
     272        pci_cfg_r32(pcidev, PCIR_COMMAND, &com1);
     273        com1 |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
     274        pci_cfg_w32(pcidev, PCIR_COMMAND, com1);
    275275
    276276        /* Start AMBA PnP scan at first AHB bus */
  • c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c

    rd5ca821 r8b29637c  
    241241
    242242        /* set parity error response */
    243         pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
    244         pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     243        pci_cfg_r32(priv->pcidev, PCIR_COMMAND, &data);
     244        pci_cfg_w32(priv->pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    245245
    246246        /* Setup cache line size. Default cache line size will result in
     
    248248         * to the max size of the PCI FIFO.
    249249         */
    250         pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff);
     250        pci_cfg_w8(priv->pcidev, PCIR_CACHELNSZ, 0xff);
    251251
    252252        /* Scan AMBA Plug&Play */
  • c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c

    rd5ca821 r8b29637c  
    275275                uint32_t data;
    276276                /* set parity error response */
    277                 pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
    278                 pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     277                pci_cfg_r32(priv->pcidev, PCIR_COMMAND, &data);
     278                pci_cfg_w32(priv->pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    279279        }
    280280#endif
     
    284284         * to the max size of the PCI FIFO.
    285285         */
    286         pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff);
     286        pci_cfg_w8(priv->pcidev, PCIR_CACHELNSZ, 0xff);
    287287
    288288        /* Scan AMBA Plug&Play */
     
    402402
    403403        /* Check capabilities list bit */
    404         pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
     404        pci_cfg_r8(pcidev, PCIR_STATUS, &tmp2);
    405405
    406406        if (!((tmp2 >> 4) & 1)) {
     
    412412
    413413        /* Read capabilities pointer */
    414         pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
     414        pci_cfg_r8(pcidev, PCIR_CAP_PTR, &cap_ptr);
    415415
    416416        /* Set AHB address mappings for target PCI bars
     
    431431#if 0
    432432        /* set parity error response */
    433         pci_cfg_r32(pcidev, PCI_COMMAND, &data);
    434         pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     433        pci_cfg_r32(pcidev, PCIR_COMMAND, &data);
     434        pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    435435#endif
    436436
  • c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c

    rd5ca821 r8b29637c  
    257257
    258258        /* Check capabilities list bit */
    259         pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
     259        pci_cfg_r8(pcidev, PCIR_STATUS, &tmp2);
    260260
    261261        if (!((tmp2 >> 4) & 1)) {
     
    265265
    266266        /* Read capabilities pointer */
    267         pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
     267        pci_cfg_r8(pcidev, PCIR_CAP_PTR, &cap_ptr);
    268268
    269269        /* Set AHB address mappings for target PCI bars */
     
    277277#if 0
    278278        /* set parity error response */
    279         pci_cfg_r32(pcidev, PCI_COMMAND, &data);
    280         pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     279        pci_cfg_r32(pcidev, PCIR_COMMAND, &data);
     280        pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    281281#endif
    282282
  • c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c

    rd5ca821 r8b29637c  
    341341                uint32_t data;
    342342                /* set parity error response */
    343                 pci_cfg_r32(pcidev, PCI_COMMAND, &data);
    344                 pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     343                pci_cfg_r32(pcidev, PCIR_COMMAND, &data);
     344                pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    345345        }
    346346#endif
     
    350350         * to the max size of the PCI FIFO.
    351351         */
    352         pci_cfg_w8(pcidev, PCI_CACHE_LINE_SIZE, 0xff);
     352        pci_cfg_w8(pcidev, PCIR_CACHELNSZ, 0xff);
    353353
    354354        /* Scan AMBA Plug&Play */
     
    443443
    444444        /* Check capabilities list bit */
    445         pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
     445        pci_cfg_r8(pcidev, PCIR_STATUS, &tmp2);
    446446
    447447        if (!((tmp2 >> 4) & 1)) {
     
    453453
    454454        /* Read capabilities pointer */
    455         pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
     455        pci_cfg_r8(pcidev, PCIR_CAP_PTR, &cap_ptr);
    456456
    457457        /* Set AHB address mappings for target PCI bars
     
    472472#if 0
    473473        /* set parity error response */
    474         pci_cfg_r32(pcidev, PCI_COMMAND, &data);
    475         pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     474        pci_cfg_r32(pcidev, PCIR_COMMAND, &data);
     475        pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN));
    476476#endif
    477477
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