source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c @ dac4208

4.104.114.84.95
Last change on this file since dac4208 was dac4208, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 31, 2004 at 3:47:07 AM

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, clock/clock.c, console/85c30.c, console/console.c, console/consolebsp.h, include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c, startup/bspstart.c, startup/genpvec.c, startup/spurious.c, startup/vmeintr.c, timer/timer.c, tod/tod.c: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 * $Id$
7 */
8
9#include <rtems.h>
10#include <assert.h>
11#include <stdio.h>
12
13#include <bsp.h>
14
15/*
16 * Forced delay to get around timing problems with the UNIVERSE chip.  The
17 * two nops are used so that the delay works for varying clock frequencies,
18 * up to 66 Mhz, with margin.  Each nop averages about 1 1/2 clock ticks,
19 * and since there are 2 nops, this routine takes about 3 clock ticks,
20 * which on a worst case 66 Mhz board, is 45 nanosecond. This time period
21 * is sufficient to guarantee a work-around to the UNIVERSE chip timing
22 * problem.  The problem is that when there are two successive accesses to
23 * an UNIVERSE register, without sufficient delay, the second access will
24 * not work correctly.
25 */
26void PCI_bus_delay ()
27{
28  asm(" nop");
29  asm(" nop");
30}
31
32
33
34/*
35 * PCI_bus_write
36 */
37void PCI_bus_write(
38  volatile uint32_t         * _addr,                  /* IN */
39  uint32_t         _data                              /* IN */
40) 
41{
42  _data = Convert_Endian_32( _data );
43  *_addr = _data;
44}
45
46uint32_t         PCI_bus_read(
47  volatile uint32_t         *  _addr                  /* IN */
48)
49{
50  uint32_t         data;
51 
52  data = *_addr;
53  data = Convert_Endian_32( data );
54  return data;
55}
56/*
57 * PCI Configuration Cycle Read/Write Access which is used to access all of
58 * devices registers on the PCI bus.  i.e.: Universe, Ethernet & PMC.
59 */
60
61uint32_t         Read_pci_device_register(
62  uint32_t         address
63)
64{
65  uint32_t         data;
66
67  /*
68   * Write the PCI configuration address
69   */
70   PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
71 
72  /*
73   *  Delay needed when running out of DRAM
74   */
75   PCI_bus_delay ();
76
77  /*
78   * read data
79   */
80  data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA );
81 
82  return data;
83}
84
85void  Write_pci_device_register(
86  uint32_t         address,
87  uint32_t         data
88)
89{
90  /*
91   * Write the PCI configuration address
92   */
93   PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
94 
95  /*
96   *  Delay needed when running out of DRAM
97   */
98   PCI_bus_delay ();
99
100  /*
101   * write data
102   */
103  PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA, data );
104}
105
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