1 | /* |
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2 | * |
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3 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. |
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4 | * On-Line Applications Research Corporation (OAR). |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #include <rtems.h> |
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10 | #include <assert.h> |
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11 | #include <stdio.h> |
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12 | |
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13 | #include <bsp.h> |
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14 | |
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15 | /* |
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16 | * Forced delay to get around timing problems with the UNIVERSE chip. The |
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17 | * two nops are used so that the delay works for varying clock frequencies, |
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18 | * up to 66 Mhz, with margin. Each nop averages about 1 1/2 clock ticks, |
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19 | * and since there are 2 nops, this routine takes about 3 clock ticks, |
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20 | * which on a worst case 66 Mhz board, is 45 nanosecond. This time period |
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21 | * is sufficient to guarantee a work-around to the UNIVERSE chip timing |
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22 | * problem. The problem is that when there are two successive accesses to |
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23 | * an UNIVERSE register, without sufficient delay, the second access will |
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24 | * not work correctly. |
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25 | */ |
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26 | void PCI_bus_delay () |
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27 | { |
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28 | asm(" nop"); |
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29 | asm(" nop"); |
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30 | } |
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31 | |
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32 | |
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33 | |
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34 | /* |
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35 | * PCI_bus_write |
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36 | */ |
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37 | void PCI_bus_write( |
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38 | volatile uint32_t * _addr, /* IN */ |
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39 | uint32_t _data /* IN */ |
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40 | ) |
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41 | { |
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42 | _data = Convert_Endian_32( _data ); |
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43 | *_addr = _data; |
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44 | } |
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45 | |
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46 | uint32_t PCI_bus_read( |
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47 | volatile uint32_t * _addr /* IN */ |
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48 | ) |
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49 | { |
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50 | uint32_t data; |
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51 | |
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52 | data = *_addr; |
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53 | data = Convert_Endian_32( data ); |
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54 | return data; |
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55 | } |
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56 | /* |
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57 | * PCI Configuration Cycle Read/Write Access which is used to access all of |
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58 | * devices registers on the PCI bus. i.e.: Universe, Ethernet & PMC. |
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59 | */ |
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60 | |
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61 | uint32_t Read_pci_device_register( |
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62 | uint32_t address |
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63 | ) |
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64 | { |
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65 | uint32_t data; |
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66 | |
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67 | /* |
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68 | * Write the PCI configuration address |
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69 | */ |
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70 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); |
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71 | |
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72 | /* |
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73 | * Delay needed when running out of DRAM |
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74 | */ |
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75 | PCI_bus_delay (); |
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76 | |
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77 | /* |
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78 | * read data |
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79 | */ |
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80 | data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA ); |
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81 | |
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82 | return data; |
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83 | } |
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84 | |
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85 | void Write_pci_device_register( |
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86 | uint32_t address, |
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87 | uint32_t data |
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88 | ) |
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89 | { |
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90 | /* |
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91 | * Write the PCI configuration address |
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92 | */ |
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93 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); |
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94 | |
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95 | /* |
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96 | * Delay needed when running out of DRAM |
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97 | */ |
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98 | PCI_bus_delay (); |
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99 | |
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100 | /* |
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101 | * write data |
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102 | */ |
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103 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA, data ); |
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104 | } |
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105 | |
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