1 | /* |
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2 | * Copyright (c) 2018 embedded brains GmbH |
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3 | * |
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4 | * Redistribution and use in source and binary forms, with or without |
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5 | * modification, are permitted provided that the following conditions |
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6 | * are met: |
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7 | * 1. Redistributions of source code must retain the above copyright |
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8 | * notice, this list of conditions and the following disclaimer. |
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9 | * 2. Redistributions in binary form must reproduce the above copyright |
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10 | * notice, this list of conditions and the following disclaimer in the |
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11 | * documentation and/or other materials provided with the distribution. |
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12 | * |
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13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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23 | * SUCH DAMAGE. |
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24 | */ |
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25 | |
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26 | #include <bsp/bootcard.h> |
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27 | #include <bsp/fatal.h> |
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28 | #include <bsp/fdt.h> |
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29 | #include <bsp/irq-generic.h> |
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30 | #include <bsp/riscv.h> |
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31 | |
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32 | #include <libfdt.h> |
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33 | #include <string.h> |
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34 | |
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35 | #if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 |
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36 | unsigned int riscv_core_freq; |
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37 | #endif |
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38 | |
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39 | void *riscv_fdt_get_address(const void *fdt, int node) |
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40 | { |
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41 | int parent; |
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42 | int ac; |
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43 | int len; |
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44 | const uint32_t *reg; |
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45 | uint64_t addr; |
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46 | |
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47 | parent = fdt_parent_offset(fdt, node); |
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48 | if (parent < 0) { |
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49 | return NULL; |
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50 | } |
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51 | |
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52 | ac = fdt_address_cells(fdt, parent); |
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53 | if (ac != 1 && ac != 2) { |
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54 | return NULL; |
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55 | } |
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56 | |
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57 | reg = fdt_getprop(fdt, node, "reg", &len); |
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58 | if (reg == NULL || len < ac) { |
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59 | return NULL; |
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60 | } |
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61 | |
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62 | addr = 0; |
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63 | |
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64 | while (ac > 0) { |
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65 | addr = (addr << 32) | fdt32_to_cpu(*reg); |
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66 | ++reg; |
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67 | --ac; |
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68 | } |
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69 | |
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70 | #if __riscv_xlen < 64 |
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71 | if (addr > 0xffffffff) { |
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72 | return NULL; |
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73 | } |
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74 | #endif |
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75 | |
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76 | return (void *)(uintptr_t) addr; |
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77 | } |
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78 | |
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79 | #ifdef RTEMS_SMP |
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80 | uint32_t riscv_hart_count; |
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81 | |
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82 | static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS]; |
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83 | #else |
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84 | static uint32_t riscv_hart_phandles[1]; |
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85 | #endif |
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86 | |
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87 | static void riscv_find_harts(void) |
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88 | { |
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89 | const void *fdt; |
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90 | int node; |
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91 | uint32_t max_hart_index; |
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92 | |
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93 | fdt = bsp_fdt_get(); |
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94 | max_hart_index = 0; |
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95 | node = -1; |
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96 | |
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97 | while ((node = fdt_node_offset_by_compatible(fdt, node, "riscv")) >= 0) { |
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98 | int subnode; |
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99 | const uint32_t *val; |
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100 | int len; |
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101 | uint32_t phandle; |
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102 | uint32_t hart_index; |
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103 | |
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104 | val = fdt_getprop(fdt, node, "reg", &len); |
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105 | if (val == NULL || len != 4) { |
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106 | bsp_fatal(RISCV_FATAL_INVALID_HART_REG_IN_DEVICE_TREE); |
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107 | } |
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108 | |
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109 | hart_index = fdt32_to_cpu(val[0]); |
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110 | |
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111 | if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) { |
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112 | continue; |
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113 | } |
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114 | |
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115 | if (hart_index > max_hart_index) { |
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116 | max_hart_index = hart_index; |
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117 | } |
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118 | |
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119 | phandle = 0; |
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120 | |
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121 | fdt_for_each_subnode(subnode, fdt, node) { |
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122 | int propoff; |
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123 | bool interrupt_controller; |
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124 | uint32_t potential_phandle; |
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125 | |
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126 | interrupt_controller = false; |
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127 | potential_phandle = 0; |
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128 | |
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129 | fdt_for_each_property_offset(propoff, fdt, subnode) { |
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130 | const char *name; |
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131 | |
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132 | val = fdt_getprop_by_offset(fdt, propoff, &name, &len); |
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133 | if (val != NULL) { |
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134 | if (strcmp(name, "interrupt-controller") == 0) { |
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135 | interrupt_controller = true; |
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136 | } else if (len == 4 && strcmp(name, "phandle") == 0) { |
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137 | potential_phandle = fdt32_to_cpu(val[0]); |
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138 | } |
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139 | } |
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140 | } |
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141 | |
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142 | if (interrupt_controller) { |
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143 | phandle = potential_phandle; |
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144 | break; |
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145 | } |
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146 | } |
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147 | |
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148 | riscv_hart_phandles[hart_index] = phandle; |
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149 | } |
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150 | |
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151 | #ifdef RTEMS_SMP |
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152 | riscv_hart_count = max_hart_index + 1; |
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153 | #endif |
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154 | } |
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155 | |
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156 | uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) |
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157 | { |
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158 | uint32_t hart_index; |
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159 | |
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160 | for (hart_index = 0; hart_index < riscv_hart_count; ++hart_index) { |
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161 | if (riscv_hart_phandles[hart_index] == phandle) { |
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162 | return hart_index; |
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163 | } |
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164 | } |
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165 | |
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166 | return UINT32_MAX; |
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167 | } |
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168 | |
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169 | #if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 |
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170 | static uint32_t get_core_frequency(void) |
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171 | { |
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172 | uint32_t node; |
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173 | const char *fdt=bsp_fdt_get(); |
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174 | |
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175 | char *tlclk; |
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176 | uint32_t len; |
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177 | |
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178 | do |
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179 | { |
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180 | node=fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); |
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181 | uint32_t *val=NULL; |
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182 | if (node>0) |
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183 | { |
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184 | tlclk = fdt_getprop(fdt, node, "clock-output-names", &len); |
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185 | |
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186 | if (strcmp(tlclk,"tlclk") == 0) |
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187 | { |
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188 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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189 | if(val !=NULL) |
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190 | { |
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191 | riscv_core_freq=fdt32_to_cpu(*val); |
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192 | break; |
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193 | } |
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194 | } |
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195 | }else |
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196 | { |
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197 | bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE); |
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198 | } |
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199 | |
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200 | } while (node > 0); |
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201 | |
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202 | return riscv_core_freq; |
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203 | } |
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204 | |
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205 | inline uint32_t riscv_get_core_frequency(void) |
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206 | { |
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207 | return riscv_core_freq; |
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208 | } |
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209 | #endif |
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210 | |
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211 | void bsp_start(void) |
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212 | { |
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213 | riscv_find_harts(); |
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214 | bsp_interrupt_initialize(); |
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215 | |
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216 | #if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 |
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217 | riscv_core_freq=get_core_frequency(); |
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218 | #endif |
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219 | |
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220 | } |
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