#3785 closed task (fixed)

Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA

Reported by: pragnesh Owned by:
Priority: normal Milestone: 5.1
Component: arch/riscv Version: 5
Severity: normal Keywords: #RISCV, #FREEDOME310, #ARTYA7
Cc: Blocked By:
Blocking:

Description


Change History (9)

comment:1 Changed on Aug 16, 2019 at 1:25:22 PM by Joel Sherrill

Please update the description of this ticket to clarify. My questions include:

  • Are you planning to submit a BSP variant for this or are you asking for one?
  • Either way please link to the hardware, manuals, etc.

comment:2 Changed on Aug 16, 2019 at 1:38:55 PM by pragnesh

Replying to Joel Sherrill:

Please update the description of this ticket to clarify. My questions include:

  • Are you planning to submit a BSP variant for this or are you asking for one?
  • Either way please link to the hardware, manuals, etc.

1) Are you planning to submit a BSP variant for this or are you asking for one?

I have already sent a patch for this new BSP varient (Freedom E310) to
devel@ rtems.org, I created this ticket so that i can give reference in the commit
message. i followed this https://docs.rtems.org/branches/master/user/support/contrib.html

Let me know, Is this a right procedure to submit a patch?

2) Either way please link to the hardware, manuals, etc.

I will update the same in description.

Last edited on Apr 16, 2020 at 11:47:04 PM by Joel Sherrill (previous) (diff)

comment:4 Changed on Oct 23, 2019 at 6:12:46 AM by Pragnesh Patel <pragnesh.patel@…>

In a7f5e42c/rtems:

riscv: add freedom E310 Arty A7 bsp

Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.

Signed-off-by: Pragnesh Patel <pragnesh.patel@…>

comment:5 Changed on Nov 14, 2019 at 10:49:33 AM by Sebastian Huber <sebastian.huber@…>

In df9426f/rtems:

bsp/riscv: riscv_get_core_frequency()

Always provide this function. Return 0 by default. Fix formatting.
Simplify function.

Update #3785.

comment:6 Changed on Nov 14, 2019 at 10:49:36 AM by Sebastian Huber <sebastian.huber@…>

In 5a1bc179/rtems:

bsp/riscv: Remove bogus Automake conditional

Update #3785.

comment:7 Changed on Nov 14, 2019 at 10:49:43 AM by Sebastian Huber <sebastian.huber@…>

In ae554670/rtems:

bsp/riscv: Fix format and warnings

Update #3785.

comment:8 Changed on Nov 29, 2019 at 7:46:02 AM by Pragnesh Patel <pragnesh.patel@…>

In f0864b3/rtems-docs:

user: Add frdme310arty BSP varient

Signed-off-by: Pragnesh Patel <pragnesh.patel@…>

Update #3785.

comment:9 Changed on Dec 12, 2019 at 5:19:47 PM by Joel Sherrill

Resolution: fixed
Status: newclosed

Closing. The BSP and user manual contents are merged. Thank you for submitting the BSP

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