Changeset a7f5e42c in rtems


Ignore:
Timestamp:
Oct 22, 2019, 10:20:05 AM (3 weeks ago)
Author:
Pragnesh Patel <pragnesh.patel@…>
Branches:
master
Children:
d4b92da2
Parents:
32c9b83
git-author:
Pragnesh Patel <pragnesh.patel@…> (10/22/19 10:20:05)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/23/19 06:11:50)
Message:

riscv: add freedom E310 Arty A7 bsp

Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.

Signed-off-by: Pragnesh Patel <pragnesh.patel@…>

Files:
3 added
7 edited

Legend:

Unmodified
Added
Removed
  • bsps/include/bsp/fatal.h

    r32c9b83 ra7f5e42c  
    153153  RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE,
    154154  RISCV_FATAL_INVALID_INTERRUPT_AFFINITY,
    155   RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE
     155  RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE,
     156  RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE
    156157} bsp_fatal_code;
    157158
  • bsps/riscv/riscv/clock/clockdrv.c

    r32c9b83 ra7f5e42c  
    131131{
    132132  int node;
    133   const uint32_t *val;
    134   int len;
     133  const fdt32_t *val;
     134  int len=0;
    135135
    136136  node = fdt_path_offset(fdt, "/cpus");
    137   val = fdt_getprop(fdt, node, "timebase-frequency", &len);
     137
     138  val = (fdt32_t *) fdt_getprop(fdt, node, "timebase-frequency", &len);
     139
    138140  if (val == NULL || len < 4) {
    139     bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
     141    int cpu0 = fdt_subnode_offset(fdt, node, "cpu@0");
     142    val = (fdt32_t *) fdt_getprop(fdt, cpu0, "timebase-frequency", &len);
     143
     144    if (val == NULL || len < 4) {
     145      bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
     146    }
    140147  }
    141 
    142148  return fdt32_to_cpu(*val);
    143149}
  • bsps/riscv/riscv/console/console-config.c

    r32c9b83 ra7f5e42c  
    2929#include <string.h>
    3030
     31#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     32#include <bsp/fe310-uart.h>
     33fe310_uart_context driver_context;
     34#endif
     35
    3136#if RISCV_ENABLE_HTIF_SUPPORT != 0
    3237static htif_console_context htif_console_instance;
     
    6065  }
    6166
     67#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     68  int root;
     69  int soc;
     70  root = fdt_path_offset(fdt, "/");
     71  soc = fdt_subnode_offset(fdt, root, "soc");
     72
     73  int offset=fdt_subnode_offset(fdt, soc,stdout_path);
     74
     75  return offset;
     76#else
    6277  return fdt_path_offset(fdt, stdout_path);
     78#endif
    6379}
    6480
     
    194210#endif
    195211
     212#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     213    if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "sifive,uart0")) {
     214      fe310_uart_context *ctx ;
     215
     216      ctx=&driver_context;
     217      ctx->regs = (uintptr_t) riscv_fdt_get_address(fdt, node);
     218      if (ctx->regs == 0)
     219      {
     220        bsp_fatal(RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE);
     221      }
     222
     223      if (node == console_node) {
     224        riscv_console.context = &ctx->base;
     225        riscv_console.putchar = fe310_console_putchar;
     226        riscv_console.getchar = fe310_uart_read;
     227      }
     228
     229      rtems_termios_device_context_initialize(&ctx->base, "FE310UART");
     230    }
     231#endif
     232
    196233    node = fdt_next_node(fdt, node, NULL);
    197234  }
     
    223260  char path[] = "/dev/ttyS?";
    224261  size_t i;
     262#endif
     263
     264#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     265  char path[] = "/dev/ttyS0";
    225266#endif
    226267
     
    256297#endif
    257298
     299#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     300  fe310_uart_context * ctx = &driver_context;
     301
     302  rtems_termios_device_install(
     303    path,
     304    &fe310_uart_handler,
     305    NULL,
     306    &ctx->base
     307  );
     308
     309  if (&ctx->base == riscv_console.context) {
     310    link(path, CONSOLE_DEVICE_NAME);
     311  }
     312
     313#endif
     314
    258315  return RTEMS_SUCCESSFUL;
    259316}
  • bsps/riscv/riscv/include/bsp/riscv.h

    r32c9b83 ra7f5e42c  
    3939void *riscv_fdt_get_address(const void *fdt, int node);
    4040
     41#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     42uint32_t riscv_get_core_frequency(void);
     43#endif
     44
    4145#ifdef RTEMS_SMP
    4246extern uint32_t riscv_hart_count;
  • bsps/riscv/riscv/start/bspstart.c

    r32c9b83 ra7f5e42c  
    3131
    3232#include <libfdt.h>
     33#include <string.h>
     34
     35#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     36unsigned int riscv_core_freq;
     37#endif
    3338
    3439void *riscv_fdt_get_address(const void *fdt, int node)
     
    162167}
    163168
     169#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     170static uint32_t get_core_frequency(void)
     171{
     172        uint32_t node;
     173        const char *fdt=bsp_fdt_get();
     174
     175  char *tlclk;
     176        uint32_t len;
     177
     178  do
     179  {
     180    node=fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
     181    uint32_t *val=NULL;
     182    if (node>0)
     183    {
     184      tlclk = fdt_getprop(fdt, node, "clock-output-names", &len);
     185
     186      if (strcmp(tlclk,"tlclk") == 0)
     187      {
     188        val = fdt_getprop(fdt, node, "clock-frequency", &len);
     189                    if(val !=NULL)
     190                    {
     191                            riscv_core_freq=fdt32_to_cpu(*val);
     192          break;
     193                    }
     194      }
     195          }else
     196    {
     197      bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE);
     198    }
     199
     200  } while (node > 0);
     201
     202        return riscv_core_freq;
     203}
     204
     205inline uint32_t riscv_get_core_frequency(void)
     206{
     207        return riscv_core_freq;
     208}
     209#endif
     210
    164211void bsp_start(void)
    165212{
    166213  riscv_find_harts();
    167214  bsp_interrupt_initialize();
    168 }
     215
     216#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     217        riscv_core_freq=get_core_frequency();
     218#endif
     219
     220}
  • c/src/lib/libbsp/riscv/riscv/Makefile.am

    r32c9b83 ra7f5e42c  
    4747
    4848# Timer
     49#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     50librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-cpucounter.c
     51#else
    4952librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-stub.c
     53#endif
    5054
    5155# IRQ
     
    6165librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/htif.c
    6266
     67#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
     68librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/fe310-uart.c
     69#endif
     70
    6371if HAS_SMP
    6472librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bspsmp.c
  • c/src/lib/libbsp/riscv/riscv/configure.ac

    r32c9b83 ra7f5e42c  
    3737RTEMS_BSPOPTS_HELP([RISCV_ENABLE_HTIF_SUPPORT],[enables the HTIF support if defined to a non-zero value, otherwise it is disabled (disabled by default)])
    3838
     39RTEMS_BSPOPTS_SET([RISCV_CONSOLE_MAX_NS16550_DEVICES],[frdme310arty*],[])
    3940RTEMS_BSPOPTS_SET([RISCV_CONSOLE_MAX_NS16550_DEVICES],[*],[2])
    4041RTEMS_BSPOPTS_HELP([RISCV_CONSOLE_MAX_NS16550_DEVICES],[maximum number of NS16550 devices supported by the console driver (2 by default)])
     42
     43RTEMS_BSPOPTS_SET([RISCV_ENABLE_FRDME310ARTY_SUPPORT],[frdme310arty*],[1])
     44RTEMS_BSPOPTS_SET([RISCV_ENABLE_FRDME310ARTY_SUPPORT],[*],[])
     45RTEMS_BSPOPTS_HELP([RISCV_ENABLE_FRDME310ARTY_SUPPORT],[enables support sifive Freedom E310 Arty board if defined to a non-zero value,otherwise it is disabled (disabled by default)])
    4146
    4247RTEMS_BSP_CLEANUP_OPTIONS
     
    5459esac
    5560
     61case "${RTEMS_BSP}" in
     62  frdm*310arty)
     63    RISCV_RAM_REGION_SIZE_DEFAULT=0x10000000
     64    ;;
     65  *)
     66    RISCV_RAM_REGION_SIZE_DEFAULT=0x04000000
     67    ;;
     68esac
     69
    5670AC_DEFUN([RISCV_LINKCMD],[
    5771AC_ARG_VAR([$1],[$2])dnl
     
    6074
    6175RISCV_LINKCMD([RISCV_RAM_REGION_BEGIN],[begin of the RAM region for linker command file (default is 0x70000000 for 64-bit with -mcmodel=medlow and 0x80000000 for all other)],[${RISCV_RAM_REGION_BEGIN_DEFAULT}])
    62 RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default 64MiB)],[0x04000000])
     76RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default is 256 MiB for frdme310arty and 64 MiB for all other)],[${RISCV_RAM_REGION_SIZE_DEFAULT}])
    6377
    6478AC_CONFIG_FILES([
Note: See TracChangeset for help on using the changeset viewer.