[7a66986] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[53dd6d61] | 4 | * @ingroup arm_beagle |
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[7a66986] | 5 | * |
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| 6 | * @brief Global BSP definitions. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2012 Claas Ziemke. All rights reserved. |
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| 11 | * |
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| 12 | * Claas Ziemke |
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| 13 | * Kernerstrasse 11 |
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| 14 | * 70182 Stuttgart |
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| 15 | * Germany |
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| 16 | * <claas.ziemke@gmx.net> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[d4edbdbc] | 20 | * http://www.rtems.org/license/LICENSE. |
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[53dd6d61] | 21 | * |
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| 22 | * Modified by Ben Gras <beng@shrike-systems.com> to add lots |
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| 23 | * of beagleboard/beaglebone definitions, delete lpc32xx specific |
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| 24 | * ones, and merge with some other header files. |
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[7a66986] | 25 | */ |
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| 26 | |
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| 27 | #ifndef LIBBSP_ARM_BEAGLE_BSP_H |
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| 28 | #define LIBBSP_ARM_BEAGLE_BSP_H |
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| 29 | |
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| 30 | #include <bspopts.h> |
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[53dd6d61] | 31 | #include <stdint.h> |
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| 32 | #include <bsp/start.h> |
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| 33 | #include <bsp/default-initial-extension.h> |
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[151e53f] | 34 | #include <bsp/beagleboneblack.h> |
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[7a66986] | 35 | |
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| 36 | #include <rtems.h> |
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[53dd6d61] | 37 | #include <rtems/irq-extension.h> |
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[7a66986] | 38 | |
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[53dd6d61] | 39 | #include <libcpu/omap3.h> |
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| 40 | #include <libcpu/am335x.h> |
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[7a66986] | 41 | |
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| 42 | #define BSP_FEATURE_IRQ_EXTENSION |
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| 43 | |
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[53dd6d61] | 44 | /* UART base clock frequency */ |
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| 45 | #define UART_CLOCK 48000000 |
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[7a66986] | 46 | |
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[53dd6d61] | 47 | /* Access memory-mapped I/O devices */ |
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| 48 | #define mmio_read(a) (*(volatile uint32_t *)(a)) |
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| 49 | #define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v)) |
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| 50 | #define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v)) |
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| 51 | #define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v)) |
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[7a66986] | 52 | |
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[53dd6d61] | 53 | #define REG16(x)(*((volatile uint16_t *)(x))) |
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| 54 | #define REG(x)(*((volatile uint32_t *)(x))) |
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[ecf62845] | 55 | #define BIT(x)(0x1 << (x)) |
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| 56 | // Start and End included |
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| 57 | #define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1)) |
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[7a66986] | 58 | |
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[53dd6d61] | 59 | #define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick())) |
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[7a66986] | 60 | |
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[53dd6d61] | 61 | /* Write a uint32_t value to a memory address. */ |
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| 62 | static inline void |
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| 63 | write32(uint32_t address, uint32_t value) |
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| 64 | { |
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| 65 | REG(address) = value; |
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| 66 | } |
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[7a66986] | 67 | |
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[53dd6d61] | 68 | /* Read an uint32_t from a memory address */ |
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| 69 | static inline uint32_t |
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| 70 | read32(uint32_t address) |
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| 71 | { |
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| 72 | return REG(address); |
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| 73 | } |
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[7a66986] | 74 | |
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[53dd6d61] | 75 | /* Set a 32 bits value depending on a mask */ |
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| 76 | static inline void |
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| 77 | set32(uint32_t address, uint32_t mask, uint32_t value) |
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| 78 | { |
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| 79 | uint32_t val; |
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| 80 | val = read32(address); |
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| 81 | /* clear the bits */ |
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| 82 | val &= ~(mask); |
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| 83 | /* apply the value using the mask */ |
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| 84 | val |= (value & mask); |
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| 85 | write32(address, val); |
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| 86 | } |
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[7a66986] | 87 | |
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[53dd6d61] | 88 | /* Write a uint16_t value to a memory address. */ |
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| 89 | static inline void |
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| 90 | write16(uint32_t address, uint16_t value) |
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| 91 | { |
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| 92 | REG16(address) = value; |
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| 93 | } |
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[7a66986] | 94 | |
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[53dd6d61] | 95 | /* Read an uint16_t from a memory address */ |
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| 96 | static inline uint16_t |
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| 97 | read16(uint32_t address) |
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[7a66986] | 98 | { |
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[53dd6d61] | 99 | return REG16(address); |
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| 100 | } |
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[7a66986] | 101 | |
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[53dd6d61] | 102 | /* Data synchronization barrier */ |
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| 103 | static inline void dsb(void) |
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| 104 | { |
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| 105 | asm volatile("dsb" : : : "memory"); |
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[7a66986] | 106 | } |
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| 107 | |
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[53dd6d61] | 108 | /* Instruction synchronization barrier */ |
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| 109 | static inline void isb(void) |
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[7a66986] | 110 | { |
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[53dd6d61] | 111 | asm volatile("isb" : : : "memory"); |
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| 112 | } |
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[7a66986] | 113 | |
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[53dd6d61] | 114 | /* flush data cache */ |
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| 115 | static inline void flush_data_cache(void) |
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| 116 | { |
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[bebfc420] | 117 | asm volatile( |
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| 118 | "mov r0, #0\n" |
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| 119 | "mcr p15, #0, r0, c7, c10, #4\n" |
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| 120 | : /* No outputs */ |
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| 121 | : /* No inputs */ |
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| 122 | : "r0","memory" |
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| 123 | ); |
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[7a66986] | 124 | } |
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| 125 | |
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[53dd6d61] | 126 | #define __arch_getb(a) (*(volatile unsigned char *)(a)) |
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| 127 | #define __arch_getw(a) (*(volatile unsigned short *)(a)) |
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| 128 | #define __arch_getl(a) (*(volatile unsigned int *)(a)) |
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| 129 | |
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| 130 | #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) |
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| 131 | #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) |
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| 132 | #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) |
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| 133 | |
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| 134 | #define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; }) |
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| 135 | #define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; }) |
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| 136 | #define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; }) |
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| 137 | |
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| 138 | #define readb(c) ({ unsigned char __v = __arch_getb(c); __v; }) |
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| 139 | #define readw(c) ({ unsigned short __v = __arch_getw(c); __v; }) |
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| 140 | #define readl(c) ({ unsigned int __v = __arch_getl(c); __v; }) |
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| 141 | |
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| 142 | #define SYSTEM_CLOCK_12 12000000 |
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| 143 | #define SYSTEM_CLOCK_13 13000000 |
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| 144 | #define SYSTEM_CLOCK_192 19200000 |
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| 145 | #define SYSTEM_CLOCK_96 96000000 |
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| 146 | |
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| 147 | #if !defined(IS_DM3730) && !defined(IS_AM335X) |
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| 148 | #error Unrecognized BSP configured. |
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[7a66986] | 149 | #endif |
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| 150 | |
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[53dd6d61] | 151 | #if IS_DM3730 |
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| 152 | #define BSP_DEVICEMEM_START 0x48000000 |
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| 153 | #define BSP_DEVICEMEM_END 0x5F000000 |
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| 154 | #endif |
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[7a66986] | 155 | |
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[53dd6d61] | 156 | #if IS_AM335X |
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| 157 | #define BSP_DEVICEMEM_START 0x44000000 |
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| 158 | #define BSP_DEVICEMEM_END 0x57000000 |
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| 159 | #endif |
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[7a66986] | 160 | |
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[53dd6d61] | 161 | /* per-target uart config */ |
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| 162 | #if IS_AM335X |
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| 163 | #define BSP_CONSOLE_UART 1 |
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| 164 | #define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1 |
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| 165 | #define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ |
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| 166 | #define BEAGLE_BASE_UART_1 0x44E09000 |
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| 167 | #define BEAGLE_BASE_UART_2 0x48022000 |
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| 168 | #define BEAGLE_BASE_UART_3 0x48024000 |
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| 169 | #endif |
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[7a66986] | 170 | |
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[53dd6d61] | 171 | /* per-target uart config */ |
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| 172 | #if IS_DM3730 |
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| 173 | #define BSP_CONSOLE_UART 3 |
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| 174 | #define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3 |
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| 175 | #define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ |
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| 176 | #define BEAGLE_BASE_UART_1 0x4806A000 |
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| 177 | #define BEAGLE_BASE_UART_2 0x4806C000 |
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| 178 | #define BEAGLE_BASE_UART_3 0x49020000 |
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| 179 | #endif |
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[7a66986] | 180 | |
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[151e53f] | 181 | /* GPIO pin config */ |
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| 182 | #if IS_AM335X |
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| 183 | #define BSP_GPIO_PIN_COUNT 128 |
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| 184 | #define BSP_GPIO_PINS_PER_BANK 32 |
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| 185 | #endif |
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| 186 | |
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| 187 | #if IS_DM3730 |
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| 188 | #define BSP_GPIO_PIN_COUNT 192 |
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| 189 | #define BSP_GPIO_PINS_PER_BANK 32 |
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| 190 | #endif |
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| 191 | |
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[f6115d7c] | 192 | #if BSP_START_COPY_FDT_FROM_U_BOOT |
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| 193 | #define BSP_FDT_IS_SUPPORTED |
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| 194 | #endif |
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| 195 | |
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[53dd6d61] | 196 | /* i2c stuff */ |
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| 197 | typedef struct { |
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| 198 | uint32_t rx_or_tx; |
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| 199 | uint32_t stat; |
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| 200 | uint32_t ctrl; |
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| 201 | uint32_t clk_hi; |
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| 202 | uint32_t clk_lo; |
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| 203 | uint32_t adr; |
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| 204 | uint32_t rxfl; |
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| 205 | uint32_t txfl; |
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| 206 | uint32_t rxb; |
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| 207 | uint32_t txb; |
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| 208 | uint32_t s_tx; |
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| 209 | uint32_t s_txfl; |
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| 210 | } beagle_i2c; |
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| 211 | |
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| 212 | /* sctlr */ |
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| 213 | /* Read System Control Register */ |
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[61c51db] | 214 | static inline uint32_t read_sctlr(void) |
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[53dd6d61] | 215 | { |
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| 216 | uint32_t ctl; |
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[7a66986] | 217 | |
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[53dd6d61] | 218 | asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t" |
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| 219 | : [ctl] "=r" (ctl)); |
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| 220 | return ctl; |
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| 221 | } |
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[7a66986] | 222 | |
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[53dd6d61] | 223 | /* Write System Control Register */ |
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| 224 | static inline void write_sctlr(uint32_t ctl) |
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| 225 | { |
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| 226 | asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t" |
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| 227 | : : [ctl] "r" (ctl)); |
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| 228 | isb(); |
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| 229 | } |
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[7a66986] | 230 | |
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[53dd6d61] | 231 | /* Read Auxiliary Control Register */ |
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[61c51db] | 232 | static inline uint32_t read_actlr(void) |
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[53dd6d61] | 233 | { |
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| 234 | uint32_t ctl; |
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[7a66986] | 235 | |
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[53dd6d61] | 236 | asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t" |
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| 237 | : [ctl] "=r" (ctl)); |
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| 238 | return ctl; |
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| 239 | } |
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[7a66986] | 240 | |
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[53dd6d61] | 241 | /* Write Auxiliary Control Register */ |
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| 242 | static inline void write_actlr(uint32_t ctl) |
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| 243 | { |
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| 244 | asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t" |
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| 245 | : : [ctl] "r" (ctl)); |
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| 246 | isb(); |
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| 247 | } |
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[7a66986] | 248 | |
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[53dd6d61] | 249 | /* Write Translation Table Base Control Register */ |
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| 250 | static inline void write_ttbcr(uint32_t bcr) |
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| 251 | { |
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| 252 | asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t" |
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| 253 | : : [bcr] "r" (bcr)); |
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[7a66986] | 254 | |
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[53dd6d61] | 255 | isb(); |
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| 256 | } |
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| 257 | |
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| 258 | /* Read Domain Access Control Register */ |
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[61c51db] | 259 | static inline uint32_t read_dacr(void) |
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[53dd6d61] | 260 | { |
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| 261 | uint32_t dacr; |
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| 262 | |
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| 263 | asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t" |
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| 264 | : [dacr] "=r" (dacr)); |
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| 265 | |
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| 266 | return dacr; |
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| 267 | } |
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| 268 | |
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| 269 | |
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| 270 | /* Write Domain Access Control Register */ |
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| 271 | static inline void write_dacr(uint32_t dacr) |
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| 272 | { |
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| 273 | asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t" |
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| 274 | : : [dacr] "r" (dacr)); |
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| 275 | |
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| 276 | isb(); |
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| 277 | } |
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| 278 | |
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| 279 | static inline void refresh_tlb(void) |
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| 280 | { |
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| 281 | dsb(); |
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| 282 | |
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| 283 | /* Invalidate entire unified TLB */ |
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| 284 | asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" |
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| 285 | : : [zero] "r" (0)); |
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| 286 | |
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| 287 | /* Invalidate all instruction caches to PoU. |
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| 288 | * Also flushes branch target cache. */ |
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| 289 | asm volatile("mcr p15, 0, %[zero], c7, c5, 0" |
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| 290 | : : [zero] "r" (0)); |
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| 291 | |
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| 292 | /* Invalidate entire branch predictor array */ |
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| 293 | asm volatile("mcr p15, 0, %[zero], c7, c5, 6" |
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| 294 | : : [zero] "r" (0)); /* flush BTB */ |
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| 295 | |
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| 296 | dsb(); |
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| 297 | isb(); |
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| 298 | } |
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| 299 | |
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| 300 | /* Read Translation Table Base Register 0 */ |
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[61c51db] | 301 | static inline uint32_t read_ttbr0(void) |
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[53dd6d61] | 302 | { |
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| 303 | uint32_t bar; |
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| 304 | |
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| 305 | asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" |
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| 306 | : [bar] "=r" (bar)); |
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| 307 | |
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| 308 | return bar & ARM_TTBR_ADDR_MASK; |
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| 309 | } |
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| 310 | |
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| 311 | |
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| 312 | /* Read Translation Table Base Register 0 */ |
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[61c51db] | 313 | static inline uint32_t read_ttbr0_unmasked(void) |
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[53dd6d61] | 314 | { |
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| 315 | uint32_t bar; |
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| 316 | |
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| 317 | asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" |
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| 318 | : [bar] "=r" (bar)); |
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| 319 | |
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| 320 | return bar; |
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| 321 | } |
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| 322 | |
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| 323 | /* Write Translation Table Base Register 0 */ |
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| 324 | static inline void write_ttbr0(uint32_t bar) |
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| 325 | { |
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| 326 | dsb(); |
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| 327 | isb(); |
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| 328 | /* In our setup TTBR contains the base address *and* the flags |
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| 329 | but other pieces of the kernel code expect ttbr to be the |
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| 330 | base address of the l1 page table. We therefore add the |
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| 331 | flags here and remove them in the read_ttbr0 */ |
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| 332 | uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED; |
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| 333 | asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t" |
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| 334 | : : [bar] "r" (v)); |
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| 335 | |
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| 336 | refresh_tlb(); |
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| 337 | } |
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| 338 | |
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| 339 | /* Behaviour on fatal error; default: test-friendly. |
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| 340 | * set breakpoint to bsp_fatal_extension. |
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[7a66986] | 341 | */ |
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[53dd6d61] | 342 | /* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */ |
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| 343 | /*#define BSP_PRESS_KEY_FOR_RESET 1 */ |
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| 344 | #define BSP_PRINT_EXCEPTION_CONTEXT 1 |
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| 345 | /* human-readable exception info */ |
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| 346 | #define BSP_RESET_BOARD_AT_EXIT 1 |
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| 347 | /* causes qemu to exit, signaling end of test */ |
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[7a66986] | 348 | |
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| 349 | |
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| 350 | /** |
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[53dd6d61] | 351 | * @defgroup arm_beagle Beaglebone, Beagleboard Support |
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[7a66986] | 352 | * |
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[53dd6d61] | 353 | * @ingroup bsp_arm |
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| 354 | * |
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| 355 | * @brief Beaglebones and beagleboards support package |
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[7a66986] | 356 | * |
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| 357 | */ |
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| 358 | |
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[53dd6d61] | 359 | /** |
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| 360 | * @brief Beagleboard specific set up of the MMU. |
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| 361 | * |
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| 362 | * Provide in the application to override. |
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| 363 | */ |
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| 364 | BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void); |
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[7a66986] | 365 | |
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[f6115d7c] | 366 | #endif /* LIBBSP_ARM_BEAGLE_BSP_H */ |
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