source: rtems/bsps/arm/beagle/include/bsp.h @ ecf62845

5
Last change on this file since ecf62845 was ecf62845, checked in by Pierre-Louis Garnier <garnie_a@…>, on 02/25/19 at 22:30:09

arm/beagle: SPI driver

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1/**
2 * @file
3 *
4 * @ingroup arm_beagle
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
11 *
12 *  Claas Ziemke
13 *  Kernerstrasse 11
14 *  70182 Stuttgart
15 *  Germany
16 *  <claas.ziemke@gmx.net>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 *
22 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
23 * of beagleboard/beaglebone definitions, delete lpc32xx specific
24 * ones, and merge with some other header files.
25 */
26
27#ifndef LIBBSP_ARM_BEAGLE_BSP_H
28#define LIBBSP_ARM_BEAGLE_BSP_H
29
30#include <bspopts.h>
31#include <stdint.h>
32#include <bsp/start.h>
33#include <bsp/default-initial-extension.h>
34#include <bsp/beagleboneblack.h>
35
36#include <rtems.h>
37#include <rtems/irq-extension.h>
38
39#include <libcpu/omap3.h>
40#include <libcpu/am335x.h>
41
42#define BSP_FEATURE_IRQ_EXTENSION
43
44/* UART base clock frequency */
45#define UART_CLOCK     48000000
46
47/* Access memory-mapped I/O devices */
48#define mmio_read(a)    (*(volatile uint32_t *)(a))
49#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
50#define mmio_set(a,v)   mmio_write((a), mmio_read((a)) | (v))
51#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
52
53#define REG16(x)(*((volatile uint16_t *)(x)))
54#define REG(x)(*((volatile uint32_t *)(x)))
55#define BIT(x)(0x1 << (x))
56// Start and End included
57#define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1))
58
59#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
60
61/* Write a uint32_t value to a memory address. */
62static inline void
63write32(uint32_t address, uint32_t value)
64{
65    REG(address) = value;
66}
67
68/* Read an uint32_t from a memory address */
69static inline uint32_t
70read32(uint32_t address)
71{
72    return REG(address);
73}
74
75/* Set a 32 bits value depending on a mask */
76static inline void
77set32(uint32_t address, uint32_t mask, uint32_t value)
78{
79    uint32_t val;
80    val = read32(address);
81    /* clear the bits */
82    val &= ~(mask);
83    /* apply the value using the mask */
84    val |= (value & mask);
85    write32(address, val);
86}
87
88/* Write a uint16_t value to a memory address. */
89static inline void
90write16(uint32_t address, uint16_t value)
91{
92    REG16(address) = value;
93}
94
95/* Read an uint16_t from a memory address */
96static inline uint16_t
97read16(uint32_t address)
98{
99    return REG16(address);
100}
101
102/* Data synchronization barrier */
103static inline void dsb(void)
104{
105    asm volatile("dsb" : : : "memory");
106}
107
108/* Instruction synchronization barrier */
109static inline void isb(void)
110{
111    asm volatile("isb" : : : "memory");
112}
113
114/* flush data cache */
115static inline void flush_data_cache(void)
116{
117    asm volatile(
118        "mov r0, #0\n"
119        "mcr p15, #0, r0, c7, c10, #4\n"
120        : /* No outputs */
121        : /* No inputs */
122        : "r0","memory"
123    );
124}
125
126#define __arch_getb(a)      (*(volatile unsigned char *)(a))
127#define __arch_getw(a)      (*(volatile unsigned short *)(a))
128#define __arch_getl(a)      (*(volatile unsigned int *)(a))
129
130#define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
131#define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
132#define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
133
134#define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
135#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
136#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
137
138#define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
139#define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
140#define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
141
142#define SYSTEM_CLOCK_12       12000000
143#define SYSTEM_CLOCK_13       13000000
144#define SYSTEM_CLOCK_192      19200000
145#define SYSTEM_CLOCK_96       96000000
146
147#if !defined(IS_DM3730) && !defined(IS_AM335X)
148#error Unrecognized BSP configured.
149#endif
150
151#if IS_DM3730
152#define BSP_DEVICEMEM_START 0x48000000
153#define BSP_DEVICEMEM_END   0x5F000000
154#endif
155
156#if IS_AM335X
157#define BSP_DEVICEMEM_START 0x44000000
158#define BSP_DEVICEMEM_END   0x57000000
159#endif
160
161/* per-target uart config */
162#if IS_AM335X
163#define BSP_CONSOLE_UART        1
164#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_1
165#define BSP_CONSOLE_UART_IRQ    OMAP3_UART1_IRQ
166#define BEAGLE_BASE_UART_1      0x44E09000
167#define BEAGLE_BASE_UART_2      0x48022000
168#define BEAGLE_BASE_UART_3      0x48024000
169#endif
170
171/* per-target uart config */
172#if IS_DM3730
173#define BSP_CONSOLE_UART        3
174#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_3
175#define BSP_CONSOLE_UART_IRQ    OMAP3_UART3_IRQ
176#define BEAGLE_BASE_UART_1      0x4806A000
177#define BEAGLE_BASE_UART_2      0x4806C000
178#define BEAGLE_BASE_UART_3      0x49020000
179#endif
180
181/* GPIO pin config */
182#if IS_AM335X
183#define BSP_GPIO_PIN_COUNT 128
184#define BSP_GPIO_PINS_PER_BANK 32
185#endif
186
187#if IS_DM3730
188#define BSP_GPIO_PIN_COUNT 192
189#define BSP_GPIO_PINS_PER_BANK 32
190#endif
191
192#if BSP_START_COPY_FDT_FROM_U_BOOT
193#define BSP_FDT_IS_SUPPORTED
194#endif
195
196/* i2c stuff */
197typedef struct {
198    uint32_t rx_or_tx;
199    uint32_t stat;
200    uint32_t ctrl;
201    uint32_t clk_hi;
202    uint32_t clk_lo;
203    uint32_t adr;
204    uint32_t rxfl;
205    uint32_t txfl;
206    uint32_t rxb;
207    uint32_t txb;
208    uint32_t s_tx;
209    uint32_t s_txfl;
210} beagle_i2c;
211
212/* sctlr */
213/* Read System Control Register */
214static inline uint32_t read_sctlr(void)
215{
216    uint32_t ctl;
217
218    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
219        : [ctl] "=r" (ctl));
220    return ctl;
221}
222
223/* Write System Control Register */
224static inline void write_sctlr(uint32_t ctl)
225{
226    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
227        : : [ctl] "r" (ctl));
228    isb();
229}
230
231/* Read Auxiliary Control Register */
232static inline uint32_t read_actlr(void)
233{
234    uint32_t ctl;
235
236    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
237            : [ctl] "=r" (ctl));
238    return ctl;
239}
240
241/* Write Auxiliary Control Register */
242static inline void write_actlr(uint32_t ctl)
243{
244    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
245        : : [ctl] "r" (ctl));
246    isb();
247}
248
249/* Write Translation Table Base Control Register */
250static inline void write_ttbcr(uint32_t bcr)
251{
252        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
253                        : : [bcr] "r" (bcr));
254
255        isb();
256}
257
258/* Read Domain Access Control Register */
259static inline uint32_t read_dacr(void)
260{
261        uint32_t dacr;
262
263        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
264                        : [dacr] "=r" (dacr));
265
266        return dacr;
267}
268
269
270/* Write Domain Access Control Register */
271static inline void write_dacr(uint32_t dacr)
272{
273        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
274                        : : [dacr] "r" (dacr));
275
276        isb();
277}
278
279static inline void refresh_tlb(void)
280{
281    dsb();
282
283    /* Invalidate entire unified TLB */
284    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
285        : : [zero] "r" (0));
286
287    /* Invalidate all instruction caches to PoU.
288     * Also flushes branch target cache. */
289    asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
290        : : [zero] "r" (0));
291
292    /* Invalidate entire branch predictor array */
293    asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
294        : : [zero] "r" (0)); /* flush BTB */
295
296    dsb();
297    isb();
298}
299
300/* Read Translation Table Base Register 0 */
301static inline uint32_t read_ttbr0(void)
302{
303    uint32_t bar;
304
305    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
306        : [bar] "=r" (bar));
307
308    return bar & ARM_TTBR_ADDR_MASK;
309}
310
311
312/* Read Translation Table Base Register 0 */
313static inline uint32_t read_ttbr0_unmasked(void)
314{
315    uint32_t bar;
316
317    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
318        : [bar] "=r" (bar));
319
320    return bar;
321}
322
323/* Write Translation Table Base Register 0 */
324static inline void write_ttbr0(uint32_t bar)
325{
326    dsb();
327    isb();
328    /* In our setup TTBR contains the base address *and* the flags
329       but other pieces of the kernel code expect ttbr to be the
330       base address of the l1 page table. We therefore add the
331       flags here and remove them in the read_ttbr0 */
332    uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
333    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
334        : : [bar] "r" (v));
335
336    refresh_tlb();
337}
338
339/* Behaviour on fatal error; default: test-friendly.
340 * set breakpoint to bsp_fatal_extension.
341 */
342/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
343/*#define  BSP_PRESS_KEY_FOR_RESET     1 */
344#define    BSP_PRINT_EXCEPTION_CONTEXT 1
345    /* human-readable exception info */
346#define    BSP_RESET_BOARD_AT_EXIT 1
347    /* causes qemu to exit, signaling end of test */
348
349
350/**
351 * @defgroup arm_beagle Beaglebone, Beagleboard Support
352 *
353 * @ingroup bsp_arm
354 *
355 * @brief Beaglebones and beagleboards support package
356 *
357 */
358
359/**
360 * @brief Beagleboard specific set up of the MMU.
361 *
362 * Provide in the application to override.
363 */
364BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
365
366#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
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