Changeset ecf62845 in rtems
- Timestamp:
- 02/25/19 22:30:09 (3 years ago)
- Branches:
- 5, master
- Children:
- 68a5f751
- Parents:
- 7abc497
- git-author:
- Pierre-Louis Garnier <garnie_a@…> (02/25/19 22:30:09)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (02/27/19 06:45:12)
- Files:
-
- 2 added
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
bsps/arm/beagle/headers.am
r7abc497 recf62845 13 13 include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/i2c.h 14 14 include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/irq.h 15 include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/spi.h -
bsps/arm/beagle/include/bsp.h
r7abc497 recf62845 53 53 #define REG16(x)(*((volatile uint16_t *)(x))) 54 54 #define REG(x)(*((volatile uint32_t *)(x))) 55 #define BIT(x)(0x1 << x) 55 #define BIT(x)(0x1 << (x)) 56 // Start and End included 57 #define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1)) 56 58 57 59 #define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick())) -
bsps/arm/include/libcpu/am335x.h
r7abc497 recf62845 19 19 #if !defined(_AM335X_H_) 20 20 #define _AM335X_H_ 21 22 #define AM335X_MASK(Shift, Width) (((1 << (Width)) - 1) << (Shift)) 23 21 24 22 25 /* Interrupt controller memory map */ … … 650 653 #define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) 651 654 #define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) 655 #define AM335X_CM_PER_SPI0_CLKCTRL (0x4c) 656 #define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE (0x2u) 657 #define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE (0x00000003u) 652 658 #define AM335X_I2C_CON_XSA (0x00000100u) 653 659 #define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA … … 661 667 662 668 /*I2C0 module clock registers*/ 663 664 669 #define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4) 665 670 #define AM335X_CM_WKUP_CLKSTCTRL (0x0) … … 675 680 #define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u) 676 681 #define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400) 682 683 /* SPI0 module clock registers */ 684 #define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u) 685 #define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u) 686 #define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST (0x00030000u) 687 677 688 678 689 /* I2C status Register */ … … 702 713 #define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF 703 714 715 716 /* SPI registers */ 717 #define AM335X_SPI0_BASE 0x48030000 718 /* SPI0 base address */ 719 #define AM335X_SPI1_BASE 0x481A0000 720 /* SPI1 base address */ 721 722 #define AM335X_SPI_REVISION 0x000 723 #define AM335X_SPI_SYSCONFIG 0x110 724 #define AM335X_SPI_SYSSTATUS 0x114 725 #define AM335X_SPI_IRQSTATUS 0x118 726 #define AM335X_SPI_IRQENABLE 0x11c 727 #define AM335X_SPI_WAKEUPENABLE 0x120 728 #define AM335X_SPI_SYST 0x124 729 #define AM335X_SPI_MODULCTRL 0x128 730 #define AM335X_SPI_CH0CONF 0x12c 731 #define AM335X_SPI_CH0STAT 0x130 732 #define AM335X_SPI_CH0CTRL 0x134 733 #define AM335X_SPI_TX0 0x138 734 #define AM335X_SPI_RX0 0x13C 735 #define AM335X_SPI_XFERLEVEL 0x17c 736 737 /* SPI sysconfig Register */ 738 #define AM335X_SPI_SYSCONFIG_SOFTRESET (1 << 1) 739 740 /* SPI sysstatus Register */ 741 #define AM335X_SPI_SYSSTATUS_RESETDONE (1 << 0) 742 743 /* SPI interrupt status Register */ 744 #define AM335X_SPI_IRQSTATUS_TX0_EMPTY (1 << 0) 745 #define AM335X_SPI_IRQSTATUS_RX0_FULL (1 << 2) 746 747 /* SPI interrupt enable Register */ 748 #define AM335X_SPI_IRQENABLE_TX0_EMPTY (1 << 0) 749 #define AM335X_SPI_IRQENABLE_RX0_FULL (1 << 2) 750 751 /* SPI system Register */ 752 #define AM335X_SPI_SYST_SPIEN_0 (1 << 0) 753 #define AM335X_SPI_SYST_SPIDAT_0 (1 << 4) 754 #define AM335X_SPI_SYST_SPIDAT_1 (1 << 5) 755 #define AM335X_SPI_SYST_SPIDATDIR0 (1 << 8) 756 #define AM335X_SPI_SYST_SPIDATDIR1 (1 << 9) 757 #define AM335X_SPI_SYST_SSB (1 << 11) 758 759 /* SPI modulctrl Register */ 760 #define AM335X_SPI_MODULCTRL_SINGLE (1 << 0) 761 #define AM335X_SPI_MODULCTRL_PIN34 (1 << 1) 762 #define AM335X_SPI_MODULCTRL_MS (1 << 2) 763 764 /* SPI Channel 0 Configuration Register */ 765 #define AM335X_SPI_CH0CONF_PHA (1 << 0) 766 #define AM335X_SPI_CH0CONF_POL (1 << 1) 767 #define AM335X_SPI_CH0CONF_CLKD_SHIFT 2 768 #define AM335X_SPI_CH0CONF_CLKD_WIDTH 4 769 #define AM335X_SPI_CH0CONF_CLKD_MASK AM335X_MASK(AM335X_SPI_CH0CONF_CLKD_SHIFT, AM335X_SPI_CH0CONF_CLKD_WIDTH) 770 #define AM335X_SPI_CH0CONF_CLKD(X) (((X) << AM335X_SPI_CH0CONF_CLKD_SHIFT) & AM335X_SPI_CH0CONF_CLKD_MASK) 771 #define AM335X_SPI_CH0CONF_EPOL (1 << 6) 772 #define AM335X_SPI_CH0CONF_WL_SHIFT 7 773 #define AM335X_SPI_CH0CONF_WL_WIDTH 5 774 #define AM335X_SPI_CH0CONF_WL_MASK AM335X_MASK(AM335X_SPI_CH0CONF_WL_SHIFT, AM335X_SPI_CH0CONF_WL_WIDTH) 775 #define AM335X_SPI_CH0CONF_WL(X) (((X) << AM335X_SPI_CH0CONF_WL_SHIFT) & AM335X_SPI_CH0CONF_WL_MASK) 776 #define AM335X_SPI_CH0CONF_TRM_SHIFT 12 777 #define AM335X_SPI_CH0CONF_TRM_WIDTH 2 778 #define AM335X_SPI_CH0CONF_TRM_MASK AM335X_MASK(AM335X_SPI_CH0CONF_TRM_SHIFT, AM335X_SPI_CH0CONF_TRM_WIDTH) 779 #define AM335X_SPI_CH0CONF_TRM(X) (((X) << AM335X_SPI_CH0CONF_TRM_SHIFT) & AM335X_SPI_CH0CONF_TRM_MASK) 780 #define AM335X_SPI_CH0CONF_DPE0 (1 << 16) 781 #define AM335X_SPI_CH0CONF_DPE1 (1 << 17) 782 #define AM335X_SPI_CH0CONF_IS (1 << 18) 783 #define AM335X_SPI_CH0CONF_FORCE (1 << 20) 784 #define AM335X_SPI_CH0CONF_SBPOL (1 << 27) 785 #define AM335X_SPI_CH0CONF_FFEW (1 << 27) 786 #define AM335X_SPI_CH0CONF_FFER (1 << 28) 787 788 /* SPI Channel 0 Status Register */ 789 #define AM335X_SPI_CH0STAT_RXS (1 << 0) 790 #define AM335X_SPI_CH0STAT_TXS (1 << 1) 791 792 /* SPI Channel 0 Control Register */ 793 #define AM335X_SPI_CH0CTRL_EN (1 << 0) 794 704 795 #endif -
c/src/lib/libbsp/arm/beagle/Makefile.am
r7abc497 recf62845 71 71 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/beagle/i2c/bbb-i2c.c 72 72 73 # SPI 74 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/beagle/spi/spi.c 75 73 76 # GPIO 74 77 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/beagle/gpio/bbb-gpio.c
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