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Ticket #4984: attach_ticket.txt

File attach_ticket.txt, 20.4 KB (added by Dario, on 01/19/24 at 12:15:41)

Attached file patchs 1Mb/s speed configuration, register mapping wrong and problem with data cache in multiframe.

Line 
1
21) the first problem was select PLLA clock at 300MHz (selecting BOARD_MCK as 150000000) in c/src/lib/libbsp/arm/atsam/configure.ac:
3
4#RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[123000000])
5RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[150000000])
6(this file is automatically generated I thing then it shold to be a problem when restart the packets download).
7
82) patch for selection clock (patch by hand made):
9
10*************************************************************************************************
11
12
13diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h
14index 7b2dc92..088effd 100644
15--- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h
16+++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h
17@@ -58,15 +58,37 @@ extern "C" {
18 #endif
19 
20 /* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */
21-#define MCAN_PROG_CLK_PRESCALER       1   /* /1 to /256 */
22+
23 // select one of the following for the programmable clock source
24 //#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_SLOW_CLK
25 //#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_MAIN_CLK
26-//#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_PLLA_CLK
27+#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_PLLA_CLK
28 //#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_UPLL_CLK
29-#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_MCK
30+//#define MCAN_PROG_CLK_SELECT          PMC_PCK_CSS_MCK
31+
32+
33+
34+
35+//should to be util use this parameter calculators:
36+// https://www.kvaser.com/support/calculators/bit-timing-calculator/
37+// https://intrepidcs.com/products/free-tools/mb-time-calculator/
38+// http://www.bittiming.can-wiki.info/
39+
40+/*
41+//con ATSAM_MCK == 123000000
42+// PLLA/HCLK/MCK clock is set to 492/246/123MHz
43+//con ATSAM_MCK == 150000000
44+// PLLA/HCLK/MCK clock is set to 300/300/150MHz
45+*/
46+
47+//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK // /* PMC_PCK_CSS_UPLL_CLK  PMC_PCK_CSS_MAIN_CLK */ PMC_PCK_CSS_MCK
48+
49+#if (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MCK)
50+// It's works at 500kb/s with multiple CAN messages
51+/**< \brief (PMC_PCK) Master Clock is selected */ // 150MHz
52+#define MCAN_PROG_CLK_PRESCALER  1
53 #define MCAN_PROG_CLK_FREQ_HZ \
54-       ((float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER)
55+       ((float)150000000 / (float)MCAN_PROG_CLK_PRESCALER )
56 
57 #define MCAN0_BIT_RATE_BPS            500000
58 #define MCAN0_PROP_SEG                2
59@@ -74,30 +96,134 @@ extern "C" {
60 #define MCAN0_PHASE_SEG2              11
61 #define MCAN0_SYNC_JUMP               4
62 
63+#define MCAN1_BIT_RATE_BPS            500000
64+#define MCAN1_PROP_SEG                2
65+#define MCAN1_PHASE_SEG1              11
66+#define MCAN1_PHASE_SEG2              11
67+#define MCAN1_SYNC_JUMP               4
68+
69+#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MAIN_CLK)
70+//doesn't work
71+/**< \brief (PMC_PCK) Main Clock is selected */
72+#define MCAN_PROG_CLK_PRESCALER      0x19
73+#define MCAN_PROG_CLK_FREQ_HZ \
74+       ((float)150000000 /*/ (float)MCAN_PROG_CLK_PRESCALER*/ )
75+
76+#define MCAN0_BIT_RATE_BPS            500000
77+#define MCAN0_PROP_SEG                8
78+#define MCAN0_PHASE_SEG1              8
79+#define MCAN0_PHASE_SEG2              8
80+#define MCAN0_SYNC_JUMP               1
81+
82+#define MCAN1_BIT_RATE_BPS            500000
83+#define MCAN1_PROP_SEG                2
84+#define MCAN1_PHASE_SEG1              11
85+#define MCAN1_PHASE_SEG2              11
86+#define MCAN1_SYNC_JUMP               4
87+
88+#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_UPLL_CLK)
89+//doesn't work
90+/**< \brief (PMC_PCK) Divided UPLL Clock is selected */ //UPLLCK (480 MHz)
91+
92+// for PCK5 PMC_PCK_CSS_UPLL_CLK
93+//#define MCAN_PROG_CLK_PRESCALER     6 // 80MHz
94+#define MCAN_PROG_CLK_PRESCALER       24
95+#define MCAN_PROG_CLK_FREQ_HZ \
96+       ((float) 480000000 /(float) MCAN_PROG_CLK_PRESCALER)
97+
98+#define MCAN0_BIT_RATE_BPS            500000
99+#define MCAN0_PROP_SEG                1
100+#define MCAN0_PHASE_SEG1              3
101+#define MCAN0_PHASE_SEG2              3
102+#define MCAN0_SYNC_JUMP               1     
103+
104+#define MCAN1_BIT_RATE_BPS            1000000
105+#define MCAN1_PROP_SEG                3
106+#define MCAN1_PHASE_SEG1              3
107+#define MCAN1_PHASE_SEG2              8
108+#define MCAN1_SYNC_JUMP               1
109+
110+#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_PLLA_CLK)
111+// it's work at 1000 kb/s (single CAN message is received)
112+
113+/**< \brief (PMC_PCK) PLLA Clock is selected */
114+
115+//PLLA // 160 - 500 MHz
116+// MainRC xtal =12MHZ -> * 0x19/1 = 300MHz
117+
118+// 300MHz(PCK) and 150MHz(MCK) by default
119+// #define PLL_MUL    0x19
120+// #define PLL_DIV    0x01
121+
122+#define MCAN_PROG_CLK_PRESCALER    10
123+#define MCAN_PROG_CLK_FREQ_HZ \
124+       ((float) 300000000 / (float) MCAN_PROG_CLK_PRESCALER)
125+
126+#define MCAN0_BIT_RATE_BPS             1000000
127+#define MCAN0_PROP_SEG                 7
128+#define MCAN0_PHASE_SEG1               4
129+#define MCAN0_PHASE_SEG2               1
130+#define MCAN0_SYNC_JUMP                1
131+
132+//StellarProject
133+#define MCAN1_BIT_RATE_BPS             1000000
134+#define MCAN1_PROP_SEG                 7
135+#define MCAN1_PHASE_SEG1               4
136+#define MCAN1_PHASE_SEG2               1
137+#define MCAN1_SYNC_JUMP                1
138+
139+/* doesn't work  @150MHz di MCK
140+#define MCAN1_PROP_SEG                 1
141+#define MCAN1_PHASE_SEG1               8
142+#define MCAN1_PHASE_SEG2               5
143+#define MCAN1_SYNC_JUMP                1
144+*/
145+#else
146+#error MCAN config no selection done
147+
148+#endif
149+
150+/*
151+#define MCAN0_BIT_RATE_BPS            500000
152+#define MCAN0_PROP_SEG                2
153+#define MCAN0_PHASE_SEG1              11
154+#define MCAN0_PHASE_SEG2              11
155+#define MCAN0_SYNC_JUMP               4
156+*/
157+
158 #define MCAN0_FAST_BIT_RATE_BPS       2000000
159 #define MCAN0_FAST_PROP_SEG           2
160 #define MCAN0_FAST_PHASE_SEG1         4
161 #define MCAN0_FAST_PHASE_SEG2         4
162 #define MCAN0_FAST_SYNC_JUMP          2
163 
164+
165+
166+
167+
168+
169+
170 #define MCAN0_NMBR_STD_FLTS           8  /* 128 max filters */
171 #define MCAN0_NMBR_EXT_FLTS           8  /* 64 max filters */
172-#define MCAN0_NMBR_RX_FIFO0_ELMTS     0  /* # of elements, 64 elements max */
173-#define MCAN0_NMBR_RX_FIFO1_ELMTS     0  /* # of elements, 64 elements max */
174+#define MCAN0_NMBR_RX_FIFO0_ELMTS     12 /* # of elements, 64 elements max */
175+#define MCAN0_NMBR_RX_FIFO1_ELMTS     12 /* # of elements, 64 elements max */
176 #define MCAN0_NMBR_RX_DED_BUF_ELMTS   16 /* # of elements, 64 elements max */
177-#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS  0  /* # of elements, 32 elements max */
178-#define MCAN0_NMBR_TX_DED_BUF_ELMTS   4  /* # of elements, 32 elements max */
179-#define MCAN0_NMBR_TX_FIFO_Q_ELMTS    0  /* # of elements, 32 elements max */
180+#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS  8  /* # of elements, 32 elements max */
181+#define MCAN0_NMBR_TX_DED_BUF_ELMTS   8  /* # of elements, 32 elements max */
182+#define MCAN0_NMBR_TX_FIFO_Q_ELMTS    4  /* # of elements, 32 elements max */
183 #define MCAN0_RX_FIFO0_ELMT_SZ        8  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
184 #define MCAN0_RX_FIFO1_ELMT_SZ        8  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
185-#define MCAN0_RX_BUF_ELMT_SZ          8  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
186-#define MCAN0_TX_BUF_ELMT_SZ          8  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
187+#define MCAN0_RX_BUF_ELMT_SZ          64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
188+#define MCAN0_TX_BUF_ELMT_SZ          32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
189+
190 
191+/*
192 #define MCAN1_BIT_RATE_BPS            500000
193 #define MCAN1_PROP_SEG                2
194 #define MCAN1_PHASE_SEG1              11
195 #define MCAN1_PHASE_SEG2              11
196 #define MCAN1_SYNC_JUMP               4
197+*/
198 
199 #define MCAN1_FAST_BIT_RATE_BPS       2000000
200 #define MCAN1_FAST_PROP_SEG           2
201@@ -107,15 +233,15 @@ extern "C" {
202 
203 #define MCAN1_NMBR_STD_FLTS           8   /* 128 max filters */
204 #define MCAN1_NMBR_EXT_FLTS           8   /* 64 max filters */
205-#define MCAN1_NMBR_RX_FIFO0_ELMTS     12  /* # of elements, 64 elements max */
206-#define MCAN1_NMBR_RX_FIFO1_ELMTS     0   /* # of elements, 64 elements max */
207-#define MCAN1_NMBR_RX_DED_BUF_ELMTS   4   /* # of elements, 64 elements max */
208-#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS  0   /* # of elements, 32 elements max */
209-#define MCAN1_NMBR_TX_DED_BUF_ELMTS   4   /* # of elements, 32 elements max */
210+#define MCAN1_NMBR_RX_FIFO0_ELMTS     64 // 12 //32 /*16*/ /*  12*/  /* # of elements, 64 elements max */
211+#define MCAN1_NMBR_RX_FIFO1_ELMTS     64 // 12 //32 /*16*/ /*0*/   /* # of elements, 64 elements max */
212+#define MCAN1_NMBR_RX_DED_BUF_ELMTS   16 /* # of elements, 64 elements max */
213+#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS  8   /* # of elements, 32 elements max */
214+#define MCAN1_NMBR_TX_DED_BUF_ELMTS   8   /* # of elements, 32 elements max */
215 #define MCAN1_NMBR_TX_FIFO_Q_ELMTS    4   /* # of elements, 32 elements max */
216-#define MCAN1_RX_FIFO0_ELMT_SZ        8   /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
217-#define MCAN1_RX_FIFO1_ELMT_SZ        8   /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
218-#define MCAN1_RX_BUF_ELMT_SZ          64  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
219+#define MCAN1_RX_FIFO0_ELMT_SZ        64 //  8 // 8   /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
220+#define MCAN1_RX_FIFO1_ELMT_SZ        64 // 8 // 8   /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
221+#define MCAN1_RX_BUF_ELMT_SZ          64 // 64  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
222 #define MCAN1_TX_BUF_ELMT_SZ          32  /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
223 
224 #ifdef __cplusplus
225
226*************************************************************************************************
227The CAN parameters used has incompatibles that calculator (but works).
228
2293) other bugs:
230*************************************************************************************************
231
232diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c
233index e91f73e..ab6ed7b 100644
234--- a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c
235+++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c
236@@ -449,7 +449,8 @@ static uint32_t can1MsgRam[MCAN1_STD_FLTS_WRDS +
237 
238 static const uint8_t dlcToMsgLength[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 };
239 
240-const MCan_ConfigType mcan0Config = {
241+//
242+/* */ const MCan_ConfigType mcan0Config = {
243        MCAN0,
244        MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) |
245        MCAN_BTP_TSEG2(MCAN0_TSEG2) | MCAN_BTP_SJW(MCAN0_SJW),
246@@ -488,7 +489,8 @@ const MCan_ConfigType mcan0Config = {
247        },
248 };
249 
250-const MCan_ConfigType mcan1Config = {
251+//
252+/* */ const MCan_ConfigType mcan1Config = {
253        MCAN1,
254        MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) |
255        MCAN_BTP_TSEG2(MCAN1_TSEG2) | MCAN_BTP_SJW(MCAN1_SJW),
256@@ -498,7 +500,7 @@ const MCan_ConfigType mcan1Config = {
257        MCAN1_NMBR_EXT_FLTS,
258        MCAN1_NMBR_RX_FIFO0_ELMTS,
259        MCAN1_NMBR_RX_FIFO1_ELMTS,
260-       MCAN0_NMBR_RX_DED_BUF_ELMTS,
261+       MCAN1_NMBR_RX_DED_BUF_ELMTS,
262        MCAN1_NMBR_TX_EVT_FIFO_ELMTS,
263        MCAN1_NMBR_TX_DED_BUF_ELMTS,
264        MCAN1_NMBR_TX_FIFO_Q_ELMTS,
265
266@@ -537,7 +539,8 @@ const MCan_ConfigType mcan1Config = {
267 *
268 * \param mcanConfig  Pointer to a MCAN instance.
269 */
270-void MCAN_Init(const MCan_ConfigType *mcanConfig)
271+// void
272+int MCAN_Init(const MCan_ConfigType *mcanConfig)
273 {
274        Mcan       *mcan = mcanConfig->pMCan;
275        uint32_t    regVal32;
276@@ -545,10 +548,31 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig)
277        uint32_t    cntr;
278        IRQn_Type   mCanLine0Irq;
279 
280+       if (mcan == MCAN0)
281+       {
282+               if ((MCAN0_BRP) > 31UL)
283+               {
284+                       printf("MCAN0_BRP=%d max value is 31", MCAN0_BRP);
285+   
286+                       return -1;
287+               }
288+       }
289+       else
290+       {
291+               if ((MCAN1_BRP) > 31UL)
292+               {
293+                       printf("MCAN1_BRP=%d max value is 31", MCAN1_BRP);
294+     
295+                       return -1;
296+               }
297+       }
298+
299+
300
301        if (MCAN0 ==  mcan) {
302@@ -574,7 +598,7 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig)
303                                                                                  0xFFFF0000);
304                mCanLine0Irq = MCAN1_IRQn;
305        } else
306-               return;
307+               return -2;
308 
309        /* Indicates Initialization state */
310        mcan->MCAN_CCCR = MCAN_CCCR_INIT_ENABLED;
311@@ -670,6 +694,8 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig)
312 
313        __DSB();
314        __ISB();
315+
316+   return 0;
317 }
318
319 /**
320@@ -741,6 +767,14 @@ void MCAN_Enable(const MCan_ConfigType *mcanConfig)
321        mcan->MCAN_CCCR &= ~MCAN_CCCR_INIT_ENABLED;
322 }
323 
324+
325+void MCAN_Disable(const MCan_ConfigType *mcanConfig)
326+{
327+       Mcan *mcan = mcanConfig->pMCan;
328+       mcan->MCAN_CCCR |= MCAN_CCCR_INIT_ENABLED;
329+}
330+
331+
332/**
333  * \brief Requests switch to Iso11898-1 (standard / classic) mode (tx & rx
334  * payloads up to 8 bytes).
335@@ -1042,7 +1076,8 @@ uint8_t MCAN_IsNewDataInRxDedBuffer(const MCan_ConfigType *mcanConfig,
336        if (buffer < 32)
337                return (mcan->MCAN_NDAT1 & (1 << buffer));
338        else if (buffer < 64)
339-               return (mcan->MCAN_NDAT1 & (1 << (buffer - 32)));
340+               // return (mcan->MCAN_NDAT1 & (1 << (buffer - 32))); // ori
341+               return (mcan->MCAN_NDAT2 & (1 << (buffer - 32)));
342        else
343                return 0;
344 }
345@@ -1095,8 +1130,8 @@ void MCAN_GetRxDedBuffer(const MCan_ConfigType *mcanConfig,
346                if (buffer < 32)
347                        mcan->MCAN_NDAT1 = (1 << buffer);
348                else
349-                       mcan->MCAN_NDAT1 = (1 << (buffer - 32));
350-
351+               //      mcan->MCAN_NDAT1 = (1 << (buffer - 32)); //ori
352+                       mcan->MCAN_NDAT2 = (1 << (buffer - 32));
353        }
354 }
355 
356@@ -1127,6 +1162,8 @@ uint32_t MCAN_GetRxFifoBuffer(const MCan_ConfigType *mcanConfig,
357        // default: fifo empty
358        fill_level = 0;
359 
360+   rtems_cache_disable_data();
361
362diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h
363index 216c3b0..bd90acb 100644
364--- a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h
365+++ b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h
366@@ -253,6 +255,11 @@ void MCAN_InitLoopback(
367 void MCAN_Enable(
368        const MCan_ConfigType *mcanConfig);
369 
370+
371+
372+void MCAN_Disable(const MCan_ConfigType *mcanConfig);
373+
374+
375 void MCAN_RequestIso11898_1(
376        const MCan_ConfigType *mcanConfig);
377
378
379diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h
380index cc11cd1..7dbb348 100644
381--- a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h
382+++ b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h
383@@ -114,13 +114,16 @@ typedef struct {
384 #define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
385 /* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
386 #define MCAN_FBTP_FSJW_Pos 0
387-#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */
388+//  #define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */
389+#define MCAN_FBTP_FSJW_Msk (0x7u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */
390 #define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))
391 #define MCAN_FBTP_FTSEG2_Pos 4
392-#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */
393+// #define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */
394+#define MCAN_FBTP_FTSEG2_Msk (0xfu << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */
395 #define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))
396 #define MCAN_FBTP_FTSEG1_Pos 8
397-#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */
398+// #define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */
399+#define MCAN_FBTP_FTSEG1_Msk (0x1fu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */
400 #define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))
401 #define MCAN_FBTP_FBRP_Pos 16
402 #define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */
403@@ -176,7 +179,7 @@ typedef struct {
404 #define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */
405 #define   MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */
406 #define   MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */
407-#define MCAN_CCCR_CME_Pos 8
408+#define MCAN_CCCR_CME_Pos 8     // FDOE+BRSE 
409 #define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */
410 #define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))
411 #define   MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */
412@@ -192,18 +195,22 @@ typedef struct {
413 #define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */
414 #define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */
415 /* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
416-#define MCAN_BTP_SJW_Pos 0
417-#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */
418+
419+//
420+#define MCAN_BTP_SJW_Pos  25
421+#define MCAN_BTP_SJW_Msk (0x7fu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */
422 #define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))
423-#define MCAN_BTP_TSEG2_Pos 4
424-#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */
425diff --git a/rtems-5/bsps/arm/atsam/start/sdram-config.c b/rtems-5/bsps/arm/atsam/start/sdram-config.c
426index f4244e1..3b82ebf 100644
427--- a/rtems-5/bsps/arm/atsam/start/sdram-config.c
428+++ b/rtems-5/bsps/arm/atsam/start/sdram-config.c
429@@ -19,7 +19,8 @@
430 #if defined ATSAM_SDRAM_IS42S16100E_7BLI
431 
432 #if ATSAM_MCK != 123000000
433-#error Please check SDRAM settings for this clock frequency.
434+// #error Please check SDRAM settings for this clock frequency.
435+#warning Please SDRAM unusable for this clock frequency.
436 #endif
437 
438 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
439@@ -45,7 +46,7 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
440 #elif defined ATSAM_SDRAM_IS42S16320F_7BL
441 
442 #if ATSAM_MCK != 123000000
443-#error Please check SDRAM settings for this clock frequency.
444+// #error Please check SDRAM settings for this clock frequency.
445 #endif
446 
447+#define MCAN_BTP_TSEG2_Pos 0
448+#define MCAN_BTP_TSEG2_Msk (0x7fu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */
449 #define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))
450 #define MCAN_BTP_TSEG1_Pos 8
451-#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */
452+#define MCAN_BTP_TSEG1_Msk (0xffu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */
453 #define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))
454 #define MCAN_BTP_BRP_Pos 16
455-#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */
456+#define MCAN_BTP_BRP_Msk (0x1ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */  //
457 #define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))
458+// End
459+
460
461diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h
462index a5fcebb..dfddb7e 100644
463--- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h
464+++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h
465@@ -431,10 +432,15 @@
466 /** Pins used for connect the smartcard */
467 #define PINS_ISO7816        PIN_USART0_TXD, PIN_USART0_SCK,PIN_ISO7816_RSTMC
468 
469+//
470+//
471+//The following code is wrong, but the re-definition of that pins in mcan.c make
472+// those errors harmless. For completeness they are reported:
473 /** MCAN0 pin Transmit Data (TXD) */
474-#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
475+//#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
476+#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
477 /** MCAN0 pin Receive Data (RXD) */
478-#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
479+//#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
480+#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
481 
482 /** MCAN1 pin Transmit Data (TXD) */
483 #define PIN_MCAN1_TXD {PIO_PC14C_CANTX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
484