1 | |
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2 | 1) the first problem was select PLLA clock at 300MHz (selecting BOARD_MCK as 150000000) in c/src/lib/libbsp/arm/atsam/configure.ac: |
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3 | |
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4 | #RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[123000000]) |
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5 | RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[150000000]) |
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6 | (this file is automatically generated I thing then it shold to be a problem when restart the packets download). |
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7 | |
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8 | 2) patch for selection clock (patch by hand made): |
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9 | |
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10 | ************************************************************************************************* |
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11 | |
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12 | |
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13 | diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h |
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14 | index 7b2dc92..088effd 100644 |
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15 | --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h |
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16 | +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h |
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17 | @@ -58,15 +58,37 @@ extern "C" { |
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18 | #endif |
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19 | |
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20 | /* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */ |
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21 | -#define MCAN_PROG_CLK_PRESCALER 1 /* /1 to /256 */ |
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22 | + |
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23 | // select one of the following for the programmable clock source |
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24 | //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_SLOW_CLK |
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25 | //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MAIN_CLK |
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26 | -//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK |
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27 | +#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK |
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28 | //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_UPLL_CLK |
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29 | -#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK |
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30 | +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK |
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31 | + |
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32 | + |
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33 | + |
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34 | + |
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35 | +//should to be util use this parameter calculators: |
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36 | +// https://www.kvaser.com/support/calculators/bit-timing-calculator/ |
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37 | +// https://intrepidcs.com/products/free-tools/mb-time-calculator/ |
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38 | +// http://www.bittiming.can-wiki.info/ |
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39 | + |
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40 | +/* |
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41 | +//con ATSAM_MCK == 123000000 |
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42 | +// PLLA/HCLK/MCK clock is set to 492/246/123MHz |
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43 | +//con ATSAM_MCK == 150000000 |
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44 | +// PLLA/HCLK/MCK clock is set to 300/300/150MHz |
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45 | +*/ |
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46 | + |
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47 | +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK // /* PMC_PCK_CSS_UPLL_CLK PMC_PCK_CSS_MAIN_CLK */ PMC_PCK_CSS_MCK |
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48 | + |
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49 | +#if (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MCK) |
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50 | +// It's works at 500kb/s with multiple CAN messages |
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51 | +/**< \brief (PMC_PCK) Master Clock is selected */ // 150MHz |
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52 | +#define MCAN_PROG_CLK_PRESCALER 1 |
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53 | #define MCAN_PROG_CLK_FREQ_HZ \ |
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54 | - ((float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER) |
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55 | + ((float)150000000 / (float)MCAN_PROG_CLK_PRESCALER ) |
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56 | |
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57 | #define MCAN0_BIT_RATE_BPS 500000 |
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58 | #define MCAN0_PROP_SEG 2 |
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59 | @@ -74,30 +96,134 @@ extern "C" { |
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60 | #define MCAN0_PHASE_SEG2 11 |
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61 | #define MCAN0_SYNC_JUMP 4 |
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62 | |
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63 | +#define MCAN1_BIT_RATE_BPS 500000 |
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64 | +#define MCAN1_PROP_SEG 2 |
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65 | +#define MCAN1_PHASE_SEG1 11 |
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66 | +#define MCAN1_PHASE_SEG2 11 |
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67 | +#define MCAN1_SYNC_JUMP 4 |
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68 | + |
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69 | +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MAIN_CLK) |
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70 | +//doesn't work |
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71 | +/**< \brief (PMC_PCK) Main Clock is selected */ |
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72 | +#define MCAN_PROG_CLK_PRESCALER 0x19 |
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73 | +#define MCAN_PROG_CLK_FREQ_HZ \ |
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74 | + ((float)150000000 /*/ (float)MCAN_PROG_CLK_PRESCALER*/ ) |
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75 | + |
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76 | +#define MCAN0_BIT_RATE_BPS 500000 |
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77 | +#define MCAN0_PROP_SEG 8 |
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78 | +#define MCAN0_PHASE_SEG1 8 |
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79 | +#define MCAN0_PHASE_SEG2 8 |
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80 | +#define MCAN0_SYNC_JUMP 1 |
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81 | + |
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82 | +#define MCAN1_BIT_RATE_BPS 500000 |
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83 | +#define MCAN1_PROP_SEG 2 |
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84 | +#define MCAN1_PHASE_SEG1 11 |
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85 | +#define MCAN1_PHASE_SEG2 11 |
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86 | +#define MCAN1_SYNC_JUMP 4 |
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87 | + |
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88 | +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_UPLL_CLK) |
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89 | +//doesn't work |
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90 | +/**< \brief (PMC_PCK) Divided UPLL Clock is selected */ //UPLLCK (480 MHz) |
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91 | + |
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92 | +// for PCK5 PMC_PCK_CSS_UPLL_CLK |
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93 | +//#define MCAN_PROG_CLK_PRESCALER 6 // 80MHz |
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94 | +#define MCAN_PROG_CLK_PRESCALER 24 |
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95 | +#define MCAN_PROG_CLK_FREQ_HZ \ |
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96 | + ((float) 480000000 /(float) MCAN_PROG_CLK_PRESCALER) |
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97 | + |
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98 | +#define MCAN0_BIT_RATE_BPS 500000 |
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99 | +#define MCAN0_PROP_SEG 1 |
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100 | +#define MCAN0_PHASE_SEG1 3 |
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101 | +#define MCAN0_PHASE_SEG2 3 |
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102 | +#define MCAN0_SYNC_JUMP 1 |
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103 | + |
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104 | +#define MCAN1_BIT_RATE_BPS 1000000 |
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105 | +#define MCAN1_PROP_SEG 3 |
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106 | +#define MCAN1_PHASE_SEG1 3 |
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107 | +#define MCAN1_PHASE_SEG2 8 |
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108 | +#define MCAN1_SYNC_JUMP 1 |
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109 | + |
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110 | +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_PLLA_CLK) |
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111 | +// it's work at 1000 kb/s (single CAN message is received) |
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112 | + |
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113 | +/**< \brief (PMC_PCK) PLLA Clock is selected */ |
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114 | + |
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115 | +//PLLA // 160 - 500 MHz |
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116 | +// MainRC xtal =12MHZ -> * 0x19/1 = 300MHz |
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117 | + |
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118 | +// 300MHz(PCK) and 150MHz(MCK) by default |
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119 | +// #define PLL_MUL 0x19 |
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120 | +// #define PLL_DIV 0x01 |
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121 | + |
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122 | +#define MCAN_PROG_CLK_PRESCALER 10 |
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123 | +#define MCAN_PROG_CLK_FREQ_HZ \ |
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124 | + ((float) 300000000 / (float) MCAN_PROG_CLK_PRESCALER) |
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125 | + |
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126 | +#define MCAN0_BIT_RATE_BPS 1000000 |
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127 | +#define MCAN0_PROP_SEG 7 |
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128 | +#define MCAN0_PHASE_SEG1 4 |
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129 | +#define MCAN0_PHASE_SEG2 1 |
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130 | +#define MCAN0_SYNC_JUMP 1 |
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131 | + |
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132 | +//StellarProject |
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133 | +#define MCAN1_BIT_RATE_BPS 1000000 |
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134 | +#define MCAN1_PROP_SEG 7 |
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135 | +#define MCAN1_PHASE_SEG1 4 |
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136 | +#define MCAN1_PHASE_SEG2 1 |
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137 | +#define MCAN1_SYNC_JUMP 1 |
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138 | + |
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139 | +/* doesn't work @150MHz di MCK |
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140 | +#define MCAN1_PROP_SEG 1 |
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141 | +#define MCAN1_PHASE_SEG1 8 |
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142 | +#define MCAN1_PHASE_SEG2 5 |
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143 | +#define MCAN1_SYNC_JUMP 1 |
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144 | +*/ |
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145 | +#else |
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146 | +#error MCAN config no selection done |
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147 | + |
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148 | +#endif |
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149 | + |
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150 | +/* |
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151 | +#define MCAN0_BIT_RATE_BPS 500000 |
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152 | +#define MCAN0_PROP_SEG 2 |
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153 | +#define MCAN0_PHASE_SEG1 11 |
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154 | +#define MCAN0_PHASE_SEG2 11 |
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155 | +#define MCAN0_SYNC_JUMP 4 |
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156 | +*/ |
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157 | + |
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158 | #define MCAN0_FAST_BIT_RATE_BPS 2000000 |
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159 | #define MCAN0_FAST_PROP_SEG 2 |
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160 | #define MCAN0_FAST_PHASE_SEG1 4 |
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161 | #define MCAN0_FAST_PHASE_SEG2 4 |
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162 | #define MCAN0_FAST_SYNC_JUMP 2 |
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163 | |
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164 | + |
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165 | + |
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166 | + |
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167 | + |
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168 | + |
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169 | + |
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170 | #define MCAN0_NMBR_STD_FLTS 8 /* 128 max filters */ |
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171 | #define MCAN0_NMBR_EXT_FLTS 8 /* 64 max filters */ |
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172 | -#define MCAN0_NMBR_RX_FIFO0_ELMTS 0 /* # of elements, 64 elements max */ |
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173 | -#define MCAN0_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ |
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174 | +#define MCAN0_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ |
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175 | +#define MCAN0_NMBR_RX_FIFO1_ELMTS 12 /* # of elements, 64 elements max */ |
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176 | #define MCAN0_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ |
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177 | -#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ |
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178 | -#define MCAN0_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ |
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179 | -#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 0 /* # of elements, 32 elements max */ |
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180 | +#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 8 /* # of elements, 32 elements max */ |
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181 | +#define MCAN0_NMBR_TX_DED_BUF_ELMTS 8 /* # of elements, 32 elements max */ |
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182 | +#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ |
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183 | #define MCAN0_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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184 | #define MCAN0_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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185 | -#define MCAN0_RX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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186 | -#define MCAN0_TX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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187 | +#define MCAN0_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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188 | +#define MCAN0_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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189 | + |
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190 | |
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191 | +/* |
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192 | #define MCAN1_BIT_RATE_BPS 500000 |
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193 | #define MCAN1_PROP_SEG 2 |
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194 | #define MCAN1_PHASE_SEG1 11 |
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195 | #define MCAN1_PHASE_SEG2 11 |
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196 | #define MCAN1_SYNC_JUMP 4 |
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197 | +*/ |
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198 | |
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199 | #define MCAN1_FAST_BIT_RATE_BPS 2000000 |
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200 | #define MCAN1_FAST_PROP_SEG 2 |
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201 | @@ -107,15 +233,15 @@ extern "C" { |
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202 | |
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203 | #define MCAN1_NMBR_STD_FLTS 8 /* 128 max filters */ |
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204 | #define MCAN1_NMBR_EXT_FLTS 8 /* 64 max filters */ |
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205 | -#define MCAN1_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ |
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206 | -#define MCAN1_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ |
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207 | -#define MCAN1_NMBR_RX_DED_BUF_ELMTS 4 /* # of elements, 64 elements max */ |
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208 | -#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ |
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209 | -#define MCAN1_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ |
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210 | +#define MCAN1_NMBR_RX_FIFO0_ELMTS 64 // 12 //32 /*16*/ /* 12*/ /* # of elements, 64 elements max */ |
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211 | +#define MCAN1_NMBR_RX_FIFO1_ELMTS 64 // 12 //32 /*16*/ /*0*/ /* # of elements, 64 elements max */ |
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212 | +#define MCAN1_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ |
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213 | +#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 8 /* # of elements, 32 elements max */ |
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214 | +#define MCAN1_NMBR_TX_DED_BUF_ELMTS 8 /* # of elements, 32 elements max */ |
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215 | #define MCAN1_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ |
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216 | -#define MCAN1_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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217 | -#define MCAN1_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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218 | -#define MCAN1_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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219 | +#define MCAN1_RX_FIFO0_ELMT_SZ 64 // 8 // 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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220 | +#define MCAN1_RX_FIFO1_ELMT_SZ 64 // 8 // 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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221 | +#define MCAN1_RX_BUF_ELMT_SZ 64 // 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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222 | #define MCAN1_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ |
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223 | |
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224 | #ifdef __cplusplus |
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225 | |
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226 | ************************************************************************************************* |
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227 | The CAN parameters used has incompatibles that calculator (but works). |
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228 | |
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229 | 3) other bugs: |
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230 | ************************************************************************************************* |
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231 | |
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232 | diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c |
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233 | index e91f73e..ab6ed7b 100644 |
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234 | --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c |
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235 | +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c |
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236 | @@ -449,7 +449,8 @@ static uint32_t can1MsgRam[MCAN1_STD_FLTS_WRDS + |
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237 | |
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238 | static const uint8_t dlcToMsgLength[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 }; |
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239 | |
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240 | -const MCan_ConfigType mcan0Config = { |
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241 | +// |
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242 | +/* */ const MCan_ConfigType mcan0Config = { |
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243 | MCAN0, |
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244 | MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) | |
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245 | MCAN_BTP_TSEG2(MCAN0_TSEG2) | MCAN_BTP_SJW(MCAN0_SJW), |
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246 | @@ -488,7 +489,8 @@ const MCan_ConfigType mcan0Config = { |
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247 | }, |
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248 | }; |
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249 | |
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250 | -const MCan_ConfigType mcan1Config = { |
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251 | +// |
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252 | +/* */ const MCan_ConfigType mcan1Config = { |
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253 | MCAN1, |
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254 | MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) | |
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255 | MCAN_BTP_TSEG2(MCAN1_TSEG2) | MCAN_BTP_SJW(MCAN1_SJW), |
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256 | @@ -498,7 +500,7 @@ const MCan_ConfigType mcan1Config = { |
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257 | MCAN1_NMBR_EXT_FLTS, |
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258 | MCAN1_NMBR_RX_FIFO0_ELMTS, |
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259 | MCAN1_NMBR_RX_FIFO1_ELMTS, |
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260 | - MCAN0_NMBR_RX_DED_BUF_ELMTS, |
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261 | + MCAN1_NMBR_RX_DED_BUF_ELMTS, |
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262 | MCAN1_NMBR_TX_EVT_FIFO_ELMTS, |
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263 | MCAN1_NMBR_TX_DED_BUF_ELMTS, |
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264 | MCAN1_NMBR_TX_FIFO_Q_ELMTS, |
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265 | |
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266 | @@ -537,7 +539,8 @@ const MCan_ConfigType mcan1Config = { |
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267 | * |
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268 | * \param mcanConfig Pointer to a MCAN instance. |
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269 | */ |
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270 | -void MCAN_Init(const MCan_ConfigType *mcanConfig) |
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271 | +// void |
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272 | +int MCAN_Init(const MCan_ConfigType *mcanConfig) |
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273 | { |
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274 | Mcan *mcan = mcanConfig->pMCan; |
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275 | uint32_t regVal32; |
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276 | @@ -545,10 +548,31 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) |
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277 | uint32_t cntr; |
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278 | IRQn_Type mCanLine0Irq; |
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279 | |
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280 | + if (mcan == MCAN0) |
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281 | + { |
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282 | + if ((MCAN0_BRP) > 31UL) |
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283 | + { |
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284 | + printf("MCAN0_BRP=%d max value is 31", MCAN0_BRP); |
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285 | + |
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286 | + return -1; |
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287 | + } |
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288 | + } |
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289 | + else |
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290 | + { |
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291 | + if ((MCAN1_BRP) > 31UL) |
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292 | + { |
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293 | + printf("MCAN1_BRP=%d max value is 31", MCAN1_BRP); |
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294 | + |
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295 | + return -1; |
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296 | + } |
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297 | + } |
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298 | + |
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299 | + |
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300 | |
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301 | if (MCAN0 == mcan) { |
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302 | @@ -574,7 +598,7 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) |
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303 | 0xFFFF0000); |
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304 | mCanLine0Irq = MCAN1_IRQn; |
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305 | } else |
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306 | - return; |
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307 | + return -2; |
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308 | |
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309 | /* Indicates Initialization state */ |
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310 | mcan->MCAN_CCCR = MCAN_CCCR_INIT_ENABLED; |
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311 | @@ -670,6 +694,8 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) |
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312 | |
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313 | __DSB(); |
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314 | __ISB(); |
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315 | + |
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316 | + return 0; |
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317 | } |
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318 | |
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319 | /** |
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320 | @@ -741,6 +767,14 @@ void MCAN_Enable(const MCan_ConfigType *mcanConfig) |
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321 | mcan->MCAN_CCCR &= ~MCAN_CCCR_INIT_ENABLED; |
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322 | } |
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323 | |
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324 | + |
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325 | +void MCAN_Disable(const MCan_ConfigType *mcanConfig) |
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326 | +{ |
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327 | + Mcan *mcan = mcanConfig->pMCan; |
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328 | + mcan->MCAN_CCCR |= MCAN_CCCR_INIT_ENABLED; |
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329 | +} |
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330 | + |
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331 | + |
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332 | /** |
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333 | * \brief Requests switch to Iso11898-1 (standard / classic) mode (tx & rx |
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334 | * payloads up to 8 bytes). |
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335 | @@ -1042,7 +1076,8 @@ uint8_t MCAN_IsNewDataInRxDedBuffer(const MCan_ConfigType *mcanConfig, |
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336 | if (buffer < 32) |
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337 | return (mcan->MCAN_NDAT1 & (1 << buffer)); |
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338 | else if (buffer < 64) |
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339 | - return (mcan->MCAN_NDAT1 & (1 << (buffer - 32))); |
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340 | + // return (mcan->MCAN_NDAT1 & (1 << (buffer - 32))); // ori |
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341 | + return (mcan->MCAN_NDAT2 & (1 << (buffer - 32))); |
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342 | else |
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343 | return 0; |
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344 | } |
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345 | @@ -1095,8 +1130,8 @@ void MCAN_GetRxDedBuffer(const MCan_ConfigType *mcanConfig, |
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346 | if (buffer < 32) |
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347 | mcan->MCAN_NDAT1 = (1 << buffer); |
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348 | else |
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349 | - mcan->MCAN_NDAT1 = (1 << (buffer - 32)); |
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350 | - |
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351 | + // mcan->MCAN_NDAT1 = (1 << (buffer - 32)); //ori |
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352 | + mcan->MCAN_NDAT2 = (1 << (buffer - 32)); |
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353 | } |
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354 | } |
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355 | |
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356 | @@ -1127,6 +1162,8 @@ uint32_t MCAN_GetRxFifoBuffer(const MCan_ConfigType *mcanConfig, |
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357 | // default: fifo empty |
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358 | fill_level = 0; |
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359 | |
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360 | + rtems_cache_disable_data(); |
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361 | |
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362 | diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h |
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363 | index 216c3b0..bd90acb 100644 |
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364 | --- a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h |
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365 | +++ b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h |
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366 | @@ -253,6 +255,11 @@ void MCAN_InitLoopback( |
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367 | void MCAN_Enable( |
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368 | const MCan_ConfigType *mcanConfig); |
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369 | |
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370 | + |
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371 | + |
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372 | +void MCAN_Disable(const MCan_ConfigType *mcanConfig); |
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373 | + |
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374 | + |
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375 | void MCAN_RequestIso11898_1( |
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376 | const MCan_ConfigType *mcanConfig); |
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377 | |
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378 | |
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379 | diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h |
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380 | index cc11cd1..7dbb348 100644 |
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381 | --- a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h |
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382 | +++ b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h |
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383 | @@ -114,13 +114,16 @@ typedef struct { |
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384 | #define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) |
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385 | /* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ |
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386 | #define MCAN_FBTP_FSJW_Pos 0 |
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387 | -#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ |
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388 | +// #define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ |
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389 | +#define MCAN_FBTP_FSJW_Msk (0x7u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ |
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390 | #define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) |
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391 | #define MCAN_FBTP_FTSEG2_Pos 4 |
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392 | -#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ |
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393 | +// #define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ |
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394 | +#define MCAN_FBTP_FTSEG2_Msk (0xfu << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ |
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395 | #define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) |
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396 | #define MCAN_FBTP_FTSEG1_Pos 8 |
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397 | -#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ |
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398 | +// #define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ |
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399 | +#define MCAN_FBTP_FTSEG1_Msk (0x1fu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ |
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400 | #define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) |
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401 | #define MCAN_FBTP_FBRP_Pos 16 |
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402 | #define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ |
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403 | @@ -176,7 +179,7 @@ typedef struct { |
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404 | #define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ |
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405 | #define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ |
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406 | #define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ |
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407 | -#define MCAN_CCCR_CME_Pos 8 |
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408 | +#define MCAN_CCCR_CME_Pos 8 // FDOE+BRSE |
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409 | #define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ |
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410 | #define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) |
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411 | #define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ |
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412 | @@ -192,18 +195,22 @@ typedef struct { |
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413 | #define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ |
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414 | #define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ |
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415 | /* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ |
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416 | -#define MCAN_BTP_SJW_Pos 0 |
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417 | -#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ |
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418 | + |
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419 | +// |
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420 | +#define MCAN_BTP_SJW_Pos 25 |
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421 | +#define MCAN_BTP_SJW_Msk (0x7fu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ |
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422 | #define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) |
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423 | -#define MCAN_BTP_TSEG2_Pos 4 |
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424 | -#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ |
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425 | diff --git a/rtems-5/bsps/arm/atsam/start/sdram-config.c b/rtems-5/bsps/arm/atsam/start/sdram-config.c |
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426 | index f4244e1..3b82ebf 100644 |
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427 | --- a/rtems-5/bsps/arm/atsam/start/sdram-config.c |
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428 | +++ b/rtems-5/bsps/arm/atsam/start/sdram-config.c |
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429 | @@ -19,7 +19,8 @@ |
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430 | #if defined ATSAM_SDRAM_IS42S16100E_7BLI |
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431 | |
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432 | #if ATSAM_MCK != 123000000 |
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433 | -#error Please check SDRAM settings for this clock frequency. |
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434 | +// #error Please check SDRAM settings for this clock frequency. |
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435 | +#warning Please SDRAM unusable for this clock frequency. |
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436 | #endif |
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437 | |
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438 | const struct BOARD_Sdram_Config BOARD_Sdram_Config = { |
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439 | @@ -45,7 +46,7 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = { |
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440 | #elif defined ATSAM_SDRAM_IS42S16320F_7BL |
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441 | |
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442 | #if ATSAM_MCK != 123000000 |
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443 | -#error Please check SDRAM settings for this clock frequency. |
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444 | +// #error Please check SDRAM settings for this clock frequency. |
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445 | #endif |
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446 | |
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447 | +#define MCAN_BTP_TSEG2_Pos 0 |
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448 | +#define MCAN_BTP_TSEG2_Msk (0x7fu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ |
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449 | #define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) |
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450 | #define MCAN_BTP_TSEG1_Pos 8 |
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451 | -#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ |
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452 | +#define MCAN_BTP_TSEG1_Msk (0xffu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ |
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453 | #define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) |
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454 | #define MCAN_BTP_BRP_Pos 16 |
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455 | -#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ |
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456 | +#define MCAN_BTP_BRP_Msk (0x1ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ // |
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457 | #define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) |
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458 | +// End |
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459 | + |
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460 | |
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461 | diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h |
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462 | index a5fcebb..dfddb7e 100644 |
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463 | --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h |
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464 | +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h |
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465 | @@ -431,10 +432,15 @@ |
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466 | /** Pins used for connect the smartcard */ |
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467 | #define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK,PIN_ISO7816_RSTMC |
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468 | |
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469 | +// |
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470 | +// |
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471 | +//The following code is wrong, but the re-definition of that pins in mcan.c make |
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472 | +// those errors harmless. For completeness they are reported: |
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473 | /** MCAN0 pin Transmit Data (TXD) */ |
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474 | -#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} |
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475 | +//#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} |
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476 | +#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} |
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477 | /** MCAN0 pin Receive Data (RXD) */ |
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478 | -#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} |
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479 | +//#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} |
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480 | +#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} |
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481 | |
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482 | /** MCAN1 pin Transmit Data (TXD) */ |
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483 | #define PIN_MCAN1_TXD {PIO_PC14C_CANTX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} |
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484 | |
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