1) the first problem was select PLLA clock at 300MHz (selecting BOARD_MCK as 150000000) in c/src/lib/libbsp/arm/atsam/configure.ac: #RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[123000000]) RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[150000000]) (this file is automatically generated I thing then it shold to be a problem when restart the packets download). 2) patch for selection clock (patch by hand made): ************************************************************************************************* diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h index 7b2dc92..088effd 100644 --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/include/mcan_config.h @@ -58,15 +58,37 @@ extern "C" { #endif /* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */ -#define MCAN_PROG_CLK_PRESCALER 1 /* /1 to /256 */ + // select one of the following for the programmable clock source //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_SLOW_CLK //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MAIN_CLK -//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK +#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK //#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_UPLL_CLK -#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK + + + + +//should to be util use this parameter calculators: +// https://www.kvaser.com/support/calculators/bit-timing-calculator/ +// https://intrepidcs.com/products/free-tools/mb-time-calculator/ +// http://www.bittiming.can-wiki.info/ + +/* +//con ATSAM_MCK == 123000000 +// PLLA/HCLK/MCK clock is set to 492/246/123MHz +//con ATSAM_MCK == 150000000 +// PLLA/HCLK/MCK clock is set to 300/300/150MHz +*/ + +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK // /* PMC_PCK_CSS_UPLL_CLK PMC_PCK_CSS_MAIN_CLK */ PMC_PCK_CSS_MCK + +#if (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MCK) +// It's works at 500kb/s with multiple CAN messages +/**< \brief (PMC_PCK) Master Clock is selected */ // 150MHz +#define MCAN_PROG_CLK_PRESCALER 1 #define MCAN_PROG_CLK_FREQ_HZ \ - ((float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER) + ((float)150000000 / (float)MCAN_PROG_CLK_PRESCALER ) #define MCAN0_BIT_RATE_BPS 500000 #define MCAN0_PROP_SEG 2 @@ -74,30 +96,134 @@ extern "C" { #define MCAN0_PHASE_SEG2 11 #define MCAN0_SYNC_JUMP 4 +#define MCAN1_BIT_RATE_BPS 500000 +#define MCAN1_PROP_SEG 2 +#define MCAN1_PHASE_SEG1 11 +#define MCAN1_PHASE_SEG2 11 +#define MCAN1_SYNC_JUMP 4 + +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_MAIN_CLK) +//doesn't work +/**< \brief (PMC_PCK) Main Clock is selected */ +#define MCAN_PROG_CLK_PRESCALER 0x19 +#define MCAN_PROG_CLK_FREQ_HZ \ + ((float)150000000 /*/ (float)MCAN_PROG_CLK_PRESCALER*/ ) + +#define MCAN0_BIT_RATE_BPS 500000 +#define MCAN0_PROP_SEG 8 +#define MCAN0_PHASE_SEG1 8 +#define MCAN0_PHASE_SEG2 8 +#define MCAN0_SYNC_JUMP 1 + +#define MCAN1_BIT_RATE_BPS 500000 +#define MCAN1_PROP_SEG 2 +#define MCAN1_PHASE_SEG1 11 +#define MCAN1_PHASE_SEG2 11 +#define MCAN1_SYNC_JUMP 4 + +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_UPLL_CLK) +//doesn't work +/**< \brief (PMC_PCK) Divided UPLL Clock is selected */ //UPLLCK (480 MHz) + +// for PCK5 PMC_PCK_CSS_UPLL_CLK +//#define MCAN_PROG_CLK_PRESCALER 6 // 80MHz +#define MCAN_PROG_CLK_PRESCALER 24 +#define MCAN_PROG_CLK_FREQ_HZ \ + ((float) 480000000 /(float) MCAN_PROG_CLK_PRESCALER) + +#define MCAN0_BIT_RATE_BPS 500000 +#define MCAN0_PROP_SEG 1 +#define MCAN0_PHASE_SEG1 3 +#define MCAN0_PHASE_SEG2 3 +#define MCAN0_SYNC_JUMP 1 + +#define MCAN1_BIT_RATE_BPS 1000000 +#define MCAN1_PROP_SEG 3 +#define MCAN1_PHASE_SEG1 3 +#define MCAN1_PHASE_SEG2 8 +#define MCAN1_SYNC_JUMP 1 + +#elif (MCAN_PROG_CLK_SELECT == PMC_PCK_CSS_PLLA_CLK) +// it's work at 1000 kb/s (single CAN message is received) + +/**< \brief (PMC_PCK) PLLA Clock is selected */ + +//PLLA // 160 - 500 MHz +// MainRC xtal =12MHZ -> * 0x19/1 = 300MHz + +// 300MHz(PCK) and 150MHz(MCK) by default +// #define PLL_MUL 0x19 +// #define PLL_DIV 0x01 + +#define MCAN_PROG_CLK_PRESCALER 10 +#define MCAN_PROG_CLK_FREQ_HZ \ + ((float) 300000000 / (float) MCAN_PROG_CLK_PRESCALER) + +#define MCAN0_BIT_RATE_BPS 1000000 +#define MCAN0_PROP_SEG 7 +#define MCAN0_PHASE_SEG1 4 +#define MCAN0_PHASE_SEG2 1 +#define MCAN0_SYNC_JUMP 1 + +//StellarProject +#define MCAN1_BIT_RATE_BPS 1000000 +#define MCAN1_PROP_SEG 7 +#define MCAN1_PHASE_SEG1 4 +#define MCAN1_PHASE_SEG2 1 +#define MCAN1_SYNC_JUMP 1 + +/* doesn't work @150MHz di MCK +#define MCAN1_PROP_SEG 1 +#define MCAN1_PHASE_SEG1 8 +#define MCAN1_PHASE_SEG2 5 +#define MCAN1_SYNC_JUMP 1 +*/ +#else +#error MCAN config no selection done + +#endif + +/* +#define MCAN0_BIT_RATE_BPS 500000 +#define MCAN0_PROP_SEG 2 +#define MCAN0_PHASE_SEG1 11 +#define MCAN0_PHASE_SEG2 11 +#define MCAN0_SYNC_JUMP 4 +*/ + #define MCAN0_FAST_BIT_RATE_BPS 2000000 #define MCAN0_FAST_PROP_SEG 2 #define MCAN0_FAST_PHASE_SEG1 4 #define MCAN0_FAST_PHASE_SEG2 4 #define MCAN0_FAST_SYNC_JUMP 2 + + + + + + #define MCAN0_NMBR_STD_FLTS 8 /* 128 max filters */ #define MCAN0_NMBR_EXT_FLTS 8 /* 64 max filters */ -#define MCAN0_NMBR_RX_FIFO0_ELMTS 0 /* # of elements, 64 elements max */ -#define MCAN0_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_FIFO1_ELMTS 12 /* # of elements, 64 elements max */ #define MCAN0_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ -#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ -#define MCAN0_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ -#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 8 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_DED_BUF_ELMTS 8 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ #define MCAN0_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ #define MCAN0_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ -#define MCAN0_RX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ -#define MCAN0_TX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ + +/* #define MCAN1_BIT_RATE_BPS 500000 #define MCAN1_PROP_SEG 2 #define MCAN1_PHASE_SEG1 11 #define MCAN1_PHASE_SEG2 11 #define MCAN1_SYNC_JUMP 4 +*/ #define MCAN1_FAST_BIT_RATE_BPS 2000000 #define MCAN1_FAST_PROP_SEG 2 @@ -107,15 +233,15 @@ extern "C" { #define MCAN1_NMBR_STD_FLTS 8 /* 128 max filters */ #define MCAN1_NMBR_EXT_FLTS 8 /* 64 max filters */ -#define MCAN1_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ -#define MCAN1_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ -#define MCAN1_NMBR_RX_DED_BUF_ELMTS 4 /* # of elements, 64 elements max */ -#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ -#define MCAN1_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_RX_FIFO0_ELMTS 64 // 12 //32 /*16*/ /* 12*/ /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_FIFO1_ELMTS 64 // 12 //32 /*16*/ /*0*/ /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 8 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_TX_DED_BUF_ELMTS 8 /* # of elements, 32 elements max */ #define MCAN1_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ -#define MCAN1_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ -#define MCAN1_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ -#define MCAN1_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_FIFO0_ELMT_SZ 64 // 8 // 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_FIFO1_ELMT_SZ 64 // 8 // 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_BUF_ELMT_SZ 64 // 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ #define MCAN1_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ #ifdef __cplusplus ************************************************************************************************* The CAN parameters used has incompatibles that calculator (but works). 3) other bugs: ************************************************************************************************* diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c index e91f73e..ab6ed7b 100644 --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libchip/source/mcan.c @@ -449,7 +449,8 @@ static uint32_t can1MsgRam[MCAN1_STD_FLTS_WRDS + static const uint8_t dlcToMsgLength[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 }; -const MCan_ConfigType mcan0Config = { +// +/* */ const MCan_ConfigType mcan0Config = { MCAN0, MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) | MCAN_BTP_TSEG2(MCAN0_TSEG2) | MCAN_BTP_SJW(MCAN0_SJW), @@ -488,7 +489,8 @@ const MCan_ConfigType mcan0Config = { }, }; -const MCan_ConfigType mcan1Config = { +// +/* */ const MCan_ConfigType mcan1Config = { MCAN1, MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) | MCAN_BTP_TSEG2(MCAN1_TSEG2) | MCAN_BTP_SJW(MCAN1_SJW), @@ -498,7 +500,7 @@ const MCan_ConfigType mcan1Config = { MCAN1_NMBR_EXT_FLTS, MCAN1_NMBR_RX_FIFO0_ELMTS, MCAN1_NMBR_RX_FIFO1_ELMTS, - MCAN0_NMBR_RX_DED_BUF_ELMTS, + MCAN1_NMBR_RX_DED_BUF_ELMTS, MCAN1_NMBR_TX_EVT_FIFO_ELMTS, MCAN1_NMBR_TX_DED_BUF_ELMTS, MCAN1_NMBR_TX_FIFO_Q_ELMTS, @@ -537,7 +539,8 @@ const MCan_ConfigType mcan1Config = { * * \param mcanConfig Pointer to a MCAN instance. */ -void MCAN_Init(const MCan_ConfigType *mcanConfig) +// void +int MCAN_Init(const MCan_ConfigType *mcanConfig) { Mcan *mcan = mcanConfig->pMCan; uint32_t regVal32; @@ -545,10 +548,31 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) uint32_t cntr; IRQn_Type mCanLine0Irq; + if (mcan == MCAN0) + { + if ((MCAN0_BRP) > 31UL) + { + printf("MCAN0_BRP=%d max value is 31", MCAN0_BRP); + + return -1; + } + } + else + { + if ((MCAN1_BRP) > 31UL) + { + printf("MCAN1_BRP=%d max value is 31", MCAN1_BRP); + + return -1; + } + } + + if (MCAN0 == mcan) { @@ -574,7 +598,7 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) 0xFFFF0000); mCanLine0Irq = MCAN1_IRQn; } else - return; + return -2; /* Indicates Initialization state */ mcan->MCAN_CCCR = MCAN_CCCR_INIT_ENABLED; @@ -670,6 +694,8 @@ void MCAN_Init(const MCan_ConfigType *mcanConfig) __DSB(); __ISB(); + + return 0; } /** @@ -741,6 +767,14 @@ void MCAN_Enable(const MCan_ConfigType *mcanConfig) mcan->MCAN_CCCR &= ~MCAN_CCCR_INIT_ENABLED; } + +void MCAN_Disable(const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_CCCR |= MCAN_CCCR_INIT_ENABLED; +} + + /** * \brief Requests switch to Iso11898-1 (standard / classic) mode (tx & rx * payloads up to 8 bytes). @@ -1042,7 +1076,8 @@ uint8_t MCAN_IsNewDataInRxDedBuffer(const MCan_ConfigType *mcanConfig, if (buffer < 32) return (mcan->MCAN_NDAT1 & (1 << buffer)); else if (buffer < 64) - return (mcan->MCAN_NDAT1 & (1 << (buffer - 32))); + // return (mcan->MCAN_NDAT1 & (1 << (buffer - 32))); // ori + return (mcan->MCAN_NDAT2 & (1 << (buffer - 32))); else return 0; } @@ -1095,8 +1130,8 @@ void MCAN_GetRxDedBuffer(const MCan_ConfigType *mcanConfig, if (buffer < 32) mcan->MCAN_NDAT1 = (1 << buffer); else - mcan->MCAN_NDAT1 = (1 << (buffer - 32)); - + // mcan->MCAN_NDAT1 = (1 << (buffer - 32)); //ori + mcan->MCAN_NDAT2 = (1 << (buffer - 32)); } } @@ -1127,6 +1162,8 @@ uint32_t MCAN_GetRxFifoBuffer(const MCan_ConfigType *mcanConfig, // default: fifo empty fill_level = 0; + rtems_cache_disable_data(); diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h index 216c3b0..bd90acb 100644 --- a/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h +++ b/rtems-5/bsps/arm/atsam/include/libchip/include/mcan.h @@ -253,6 +255,11 @@ void MCAN_InitLoopback( void MCAN_Enable( const MCan_ConfigType *mcanConfig); + + +void MCAN_Disable(const MCan_ConfigType *mcanConfig); + + void MCAN_RequestIso11898_1( const MCan_ConfigType *mcanConfig); diff --git a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h index cc11cd1..7dbb348 100644 --- a/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h +++ b/rtems-5/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h @@ -114,13 +114,16 @@ typedef struct { #define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) /* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ #define MCAN_FBTP_FSJW_Pos 0 -#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +// #define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW_Msk (0x7u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ #define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) #define MCAN_FBTP_FTSEG2_Pos 4 -#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +// #define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2_Msk (0xfu << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ #define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) #define MCAN_FBTP_FTSEG1_Pos 8 -#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +// #define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1_Msk (0x1fu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ #define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) #define MCAN_FBTP_FBRP_Pos 16 #define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ @@ -176,7 +179,7 @@ typedef struct { #define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ #define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ #define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ -#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Pos 8 // FDOE+BRSE #define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ #define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) #define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ @@ -192,18 +195,22 @@ typedef struct { #define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ #define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ /* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ -#define MCAN_BTP_SJW_Pos 0 -#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ + +// +#define MCAN_BTP_SJW_Pos 25 +#define MCAN_BTP_SJW_Msk (0x7fu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ #define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) -#define MCAN_BTP_TSEG2_Pos 4 -#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ diff --git a/rtems-5/bsps/arm/atsam/start/sdram-config.c b/rtems-5/bsps/arm/atsam/start/sdram-config.c index f4244e1..3b82ebf 100644 --- a/rtems-5/bsps/arm/atsam/start/sdram-config.c +++ b/rtems-5/bsps/arm/atsam/start/sdram-config.c @@ -19,7 +19,8 @@ #if defined ATSAM_SDRAM_IS42S16100E_7BLI #if ATSAM_MCK != 123000000 -#error Please check SDRAM settings for this clock frequency. +// #error Please check SDRAM settings for this clock frequency. +#warning Please SDRAM unusable for this clock frequency. #endif const struct BOARD_Sdram_Config BOARD_Sdram_Config = { @@ -45,7 +46,7 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = { #elif defined ATSAM_SDRAM_IS42S16320F_7BL #if ATSAM_MCK != 123000000 -#error Please check SDRAM settings for this clock frequency. +// #error Please check SDRAM settings for this clock frequency. #endif +#define MCAN_BTP_TSEG2_Pos 0 +#define MCAN_BTP_TSEG2_Msk (0x7fu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ #define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) #define MCAN_BTP_TSEG1_Pos 8 -#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1_Msk (0xffu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ #define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) #define MCAN_BTP_BRP_Pos 16 -#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP_Msk (0x1ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ // #define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +// End + diff --git a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h index a5fcebb..dfddb7e 100644 --- a/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h +++ b/rtems-5/bsps/arm/atsam/contrib/libraries/libboard/board_v71_xult.h @@ -431,10 +432,15 @@ /** Pins used for connect the smartcard */ #define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK,PIN_ISO7816_RSTMC +// +// +//The following code is wrong, but the re-definition of that pins in mcan.c make +// those errors harmless. For completeness they are reported: /** MCAN0 pin Transmit Data (TXD) */ -#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +//#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} /** MCAN0 pin Receive Data (RXD) */ -#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +//#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} /** MCAN1 pin Transmit Data (TXD) */ #define PIN_MCAN1_TXD {PIO_PC14C_CANTX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}