Changes between Version 5 and Version 6 of TBR/UserManual/RTEMS_SIMD_Support

Timestamp:

03/31/11 22:26:28 (13 years ago)

Author:

JoelSherrill

Comment:

/* SIMD Support in RTEMS */

TBR/UserManual/RTEMS_SIMD_Support

@@ -10 +10 @@
  *  The toolchain must offer a matching multilib variant (either for the CPU model selected by the BSP or for the explicit SIMD flag(s) - which would also have to be requested by the BSP's CPU_CFLAGS).
 
-   Note that it is a very bad idea to link code compiled with different SIMD settings (enabled vs. disabled) together. The same is true
-   for hard- and soft-floating point code. While mixing such code might seem to 'just work' it actually may introduce subtle ABI
-   incompatibilities that can lead to rare and mysterious run-time errors.
+Note that it is a very bad idea to link code compiled with different SIMD settings (enabled vs. disabled) together. The same is true for hard- and soft-floating point code. While mixing such code might seem to 'just work' it actually may introduce subtle ABI incompatibilities that can lead to rare and mysterious run-time errors.
 
-It should be noted that executing code that was built for a particular SIMD engine on hardware that doesn't actually have this engine will crash.
-If you e.g., build a pcx86 BSP with -march=pentium4 (which implies -msse and -msse2) then you cannot use this BSP on a machine that only has SSE
-(but not SSE2).
+'''It should be noted that executing code that was built for a particular SIMD engine on hardware that doesn't actually have this engine will crash.If you e.g., build a pcx86 BSP with -march=pentium4 (which implies -msse and -msse2) then you cannot use this BSP on a machine that only has SSE (but not SSE2).'''
 =  AltiVec and PowerPC  =