RTEMS SIMD Support

SIMD Support in RTEMS

As of release 4.10 RTEMS supports managing the SIMD registers on select CPU architectures. I.e., SIMD registers are preserved across context switches and exceptions/interrupts. The support is automatically enabled if RTEMS is compiled for a CPU which features SIMD hardware. This is accomplished by using standardized CPP macros that are set by gcc when it generates code for a SIMD-capable CPU. E.g., when compiling for a 7400 powerpc (which has AltiVec?) or explicitly requesting AltiVec? (gcc's -maltivec flag) then gcc pre-defines the CPP macro ALTIVEC.

Hence, for properly building RTEMS with SIMD support

• The BSP's make/custom/<bsp>.cfg file must specify gcc flags that enable SIMD support, either implicitly (by selecting an appropriate CPU model) or explicitly (by enabling e.g., -maltivec or -msse2).
• The toolchain must offer a matching multilib variant (either for the CPU model selected by the BSP or for the explicit SIMD flag(s) - which would also have to be requested by the BSP's CPU_CFLAGS).

Note that it is a very bad idea to link code compiled with different SIMD settings (enabled vs. disabled) together. The same is true for hard- and soft-floating point code. While mixing such code might seem to 'just work' it actually may introduce subtle ABI incompatibilities that can lead to rare and mysterious run-time errors.

It should be noted that executing code that was built for a particular SIMD engine on hardware that doesn't actually have this engine will crash.If you e.g., build a pcx86 BSP with -march=pentium4 (which implies -msse and -msse2) then you cannot use this BSP on a machine that only has SSE (but not SSE2).

AltiVec? and PowerPC

Luckily the RTEMS pre-built toolchain comes with a -mcpu=7400 multilib variant (which implicitly enables AltiVec?).

The beatnik BSP

However, the only BSP that currently uses this variant (and due to the CPP macro ALTIVEC being defined enables RTEMS' AltiVec? support at compile-time) is the 'beatnik' BSP (for the mvme6100 and mvme5500 boards). If you use this BSP under rtems-4.10 then you already use AltiVec?.

Using AltiVec? on PSIM

Interestingly, PSIM also supports AltiVec? and it is straight-forward to (re-)build the psim BSP with AltiVec? support enabled:

• Edit the file make/custom/psim.cfg in the BSP subdirectory and change the -mcpu=powerpc setting in CPU_CFLAGS to -mcpu=7400. You probably have to do this before running 'configure'. You then simply configure and build RTEMS.
• On the PSIM side you also have some work to do. First of all, you need to apply the patch File:gdb-7.1-psim-altivec-fixes-1a.diff? to gdb-7.1 because PSIM's AltiVec? support unfortunately has quite a few bugs.
• You must rebuild gdb-7.1/psim with altivec support enabled. You request this at configure-time using the configure option --enable-sim-float=altivec= Using SSE(1/2/3) on i386 =

Unfortunately, on this architecture you are out of luck when using the pre-built RTEMS-4.10 toolchain. The multilib variants (and there are quite a few) only differ in their '-mtune' option settings which don't really do anything worthwhile (they still stick to the i386 instruction set). So you need to

• Build your own gcc/newlib. You must download the sources and apply all the RTEMS patches. Hopefully you can simply use a SRPM. Then you go to the 'gcc/config/i386' subdirectory and edit the file 't-rtems-i386'. Replace all occurrences of 'mtune=pentiumpro' by 'march=pentium4' and 'mpentiumpro' by 'mpentium4'. You must do this edit "before" configuring and building the cross-compiler. Double-check for typos or you'll encounter problems after a lengthy build process.
• Edit make/custom/pc686.cfg and replace 'mtune=pentiumpro' by 'march=pentium4'. Then you can configure and build RTEMS for the pc686 BSP.