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Changes between Version 5 and Version 6 of TBR/BSP/Phycore_mpc5554


Ignore:
Timestamp:
03/24/14 00:04:48 (10 years ago)
Author:
Dufault
Comment:

Legend:

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  • TBR/BSP/Phycore_mpc5554

    v5 v6  
    1010|NVMEM        =Chip: 2MB flash; Board: Up to 8MB flash
    1111|Architecture = PowerPC
    12 |Peripherals = Chip: 2 eTPU, 4 dSPI, 2 eSCI, 3 flexCAN, 2 12-bit ADC with 40 inputs; Board: SMC ethernet, Lattice FPGA
     12|Peripherals = Chip: 2 eTPU, 4 dSPI, 3 flexCAN, 2 12-bit ADC with 40 inputs; Board: SMC ethernet, Lattice FPGA
     13|Serial Ports = 2 eSCI
    1314|Board_URL    = http://www.phytec.com/products/som/PowerPC/phyCORE-MPC5554.html
    1415