Phycore mpc5554

Infobox BSP

BSP_name phyCORE-MPC5554
Manufacturer Chip: Freescale; Board: PHYTEC
image PhyCORE.jpg
CPU_model MPC5554 (e200z6), up to 132 MHz CPU speed
RAM Chip: 64 kByte SRAM with 32 kByte capable of battery buffering; Board: Up to 16MB SRAM
NVMEM Chip: 2MB flash; Board: Up to 8MB flash
Architecture PowerPC
Peripherals Chip: 2 eTPU, 4 dSPI, 3 flexCAN, 2 12-bit ADC with 40 inputs; Board: SMC ethernet, Lattice FPGA
Serial Ports 2 eSCI

The phyCORE-MPC5554 belongs to PHYTEC’s phyCORE Single Board Computer module family. The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments. = Overview =

The Freescale MPC5554 PowerPC microcontroller embodies the continued development of the successful MPC500 family. This device expands upon the functions and features of the MPC565 by offering enhanced eTPU and eQADC, as well as more than doubling the clock frequency to 132MHz and introducing an Instruction Cache while requiring a low 1V5 core power supply. 5V, 3V3 and 1V5 core supply voltages are generated on-board. The MPC5554 offers system performance of up to five times higher than its MPC500 predecessors. It offers 2 MB on-chip Flash memory, enhanced timer systems, and a peripheral set tailored for automotive and industrial applications. Based on the PowerPC architecture and instruction set, the MPC5554 32-bit embedded controller has been designed for real-time control applications such as automotive powertrain systems.

As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference) problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package. The increased pin package allows dedication of approximately 20 % of all pin header connectors on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments.

phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0402-packaged SMD and laser-drilled Microvias components are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE-MPC5554 is a subminiature (84 x 57 mm) insert-ready Single Board Computer populated with Freescale's PowerPC MPC5554 microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density (0.635 mm) Molex pin header connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a target application= System Start-Up Configuration =

The phyCORE-MPC5554 supports four different software start-up modes:

  • Internal Flash Memory
  • External Memory controlled by /CS0
  • FlexCAN = Internal/External? Memory Boot =

The decision which mode is used after /RESET goes from active to inactive state is defined by the external signal /RSTCFG (X2C9). The default state of this signal is high configured by an on-board pull-up resistor to VDD3V3. = Features =

The phyCORE-MPC5554 offers the following features:

  • Single Board Computer in subminiature form factor (84 x 57 mm) according to phyCORE specifications
  • all applicable controller and other logic signals extend to two highdensity 200-pin Molex connectors
  • processor: Freescale embedded PowerPC MPC5554 (up to 132 MHz clock)

Internal Features of the MPC5554:

  • 32-bit PowerPC core, up to 132 MHz CPU speed
  • 32 kByte Cache memory
  • SPE Signal Processing Extention (FPU, MAC Unit)
  • Memory Management Unit (MMU)
  • Direct Memory Access (DMA) controller
  • Interrupt latency <70ns @132MHz
  • 64 kByte SRAM; 32 kByte capable of battery buffering
  • 2 MByte Flash (read while write functionality)
  • two UART's (eSCI), LIN support
  • four SPI interfaces (DSPI)
  • three CAN 2.0B interfaces
  • two Time Processing Units (TPU) with 32 channels (pins) each
  • 24 channels (pins) timer system (eMIOS) for PWM etc.
  • dual 12-bit ADC with 40 (65) channels (ext. MUX)
  • multi-purpose I/O signals
  • JTAG/OnCE/Nexus test/debug port

Memory Configuration:

  • SRAM: 1 MByte to 16 MByte flow-through synchronous burstRAM, 32-bit access, 0 wait states, 2-1-1-1 burst mode
  • Flash: 2 MByte to 8 MByte asynchronous standard Flash, 32-bit access
  • I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C FRAM, I2C SRAM)

Other Board-Level Features:

  • UART: two RS-232 transceivers for channel A and B (RxD/TxD), also configurable as TTL
  • CAN: two 82C250-compatible CAN transceivers for channels A and B; also configurable as TTL
  • Ethernet: 10/100 Mbit/s LAN91C111
  • FPGA: Lattice XP FPGA XP6/10/15 or XP20 device for IP cores: e.g. I2C Master, 1-Wire-Master, UART, SPI etc.

programmable bus bridge (simple address-/data bus, PCI bus, DDR-RAM etc.) 84 external GPIO with programmable characteristics (TTL, CMOS, differential logic, LVDS etc.) application specific control logic and clock generation (PLL) embedded memory: single-/dual-port SRAM, FIFO etc. in-system programmable over JTAG emulation

  • I2C Real-Time Clock with calendar and alarm function
  • JTAG/OnCE/Nexus test/debug port
  • industrial temperature range (-40…+85°C= System Memory =

The system memory consist of internal MPC5554 Flash memory, external standard Flash memory, Synchronous Burst SRAM and a small non-volatile memory device:

  • 2 MByte internal MPC5554 Flash (read while write functionality)
  • 2 MByte to 8 MByte asynchronous standard Flash-EEPROM, 32-bit access
  • 1 MByte to 16 MByte flow-through synchronous Burst SRAM, 32-bit access, 0 wait states, 2-1-1-1 burst mode
  • I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C FRAM, I2C SRAM)

The external Flash and sync. SRAM are connected to the MPC5554 32-bit data bus. The Flash is controlled by /CS0 for boot operation. The Synchronous Burst SRAM is controlled by /CS1 and supports the special synchronous burst modes that enables maximum data transfer rates. Communication with the small non-volatile memory device (EPROM, FRAM or SRAM) is established over the I2C bus. This memory device can be used for storage of system parameters or configuration data


Last modified on Nov 8, 2018 at 10:09:43 PM Last modified on Nov 8, 2018, 10:09:43 PM