Changes between Version 1 and Version 2 of TBR/BSP/Phycore_mpc5554

Timestamp:

12/17/11 04:09:29 (13 years ago)

Author:

Vladimir Stankulov

Comment:

TBR/BSP/Phycore_mpc5554

@@ -8 +8 @@
 |CPU_model    = MPC5554, up to 132 MHz CPU speed
 |RAM          = 64 kByte SRAM; 32 kByte capable of battery buffering
+|NVMEM        =EEPROM, FRAM or SRAM.The capacity ranges from 512 Byte to 32 kByte or more
 |Architecture = PowerPC
 |Board_URL    = http://www.phytec.com/products/som/PowerPC/phyCORE-MPC5554.html
@@ -36 +37 @@
 inactive state is defined by the external signal /RSTCFG (X2C9). The 
 default state of this signal is high configured by an on-board pull-up 
-resistor to VDD3V3. 
-= System Memory =
+resistor to VDD3V3. = Features =
+
+The phyCORE-MPC5554 offers the following features: 
+ *  Single Board Computer in subminiature form factor (84 x 57 mm) according to phyCORE specifications 
+ *  all applicable controller and other logic signals extend to two highdensity 200-pin Molex connectors 
+ *  processor: Freescale embedded PowerPC MPC5554 (up to 132 MHz clock) 
+Internal Features of the MPC5554: 
+ *  32-bit PowerPC core, up to 132 MHz CPU speed 
+ *  32 kByte Cache memory 
+ *  SPE Signal Processing Extention (FPU, MAC Unit) 
+ *  Memory Management Unit (MMU) 
+ *  Direct Memory Access (DMA) controller 
+ *  Interrupt latency <70ns @132MHz 
+ *  64 kByte SRAM; 32 kByte capable of battery buffering 
+ *  2 MByte Flash (read while write functionality) 
+ *  two UART's (eSCI), LIN support 
+ *  four SPI interfaces (DSPI) 
+ *  three CAN 2.0B interfaces 
+ *  two Time Processing Units (TPU) with 32 channels (pins) each 
+ *  24 channels (pins) timer system (eMIOS) for PWM etc. 
+ *  dual 12-bit ADC with 40 (65) channels (ext. MUX) 
+ *  multi-purpose I/O signals 
+ *  JTAG/OnCE/Nexus test/debug port
+
+
+Memory Configuration: 
+ *  SRAM: 1 MByte to 16 MByte flow-through synchronous burstRAM, 32-bit access, 0 wait states, 2-1-1-1 burst mode 
+ *  Flash: 2 MByte to 8 MByte asynchronous standard Flash, 32-bit access 
+ *  I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C FRAM, I2C SRAM) 
+Other Board-Level Features: 
+ *  UART: two RS-232 transceivers for channel A and B (RxD/TxD), also configurable as TTL 
+ *  CAN: two 82C250-compatible CAN transceivers for channels A and B; also configurable as TTL 
+ *  Ethernet: 10/100 Mbit/s LAN91C111 
+ *  FPGA: Lattice XP FPGA XP6/10/15 or XP20 device for IP cores: e.g. I2C Master, 1-Wire-Master, UART, SPI etc. 
+programmable bus bridge (simple address-/data bus, PCI bus, DDR-RAM etc.) 
+84 external GPIO with programmable characteristics (TTL, CMOS, differential logic, LVDS etc.) 
+application specific control logic and clock generation (PLL) 
+embedded memory: single-/dual-port SRAM, FIFO etc. 
+in-system programmable over JTAG emulation 
+ *  I2C Real-Time Clock with calendar and alarm function 
+ *  JTAG/OnCE/Nexus test/debug port 
+ *  industrial temperature range (-40…+85°C= System Memory =