Changes between Initial Version and Version 1 of TBR/BSP/Phycore_mpc5554

Timestamp:

12/17/11 04:01:09 (13 years ago)

Author:

Vladimir Stankulov

Comment:

Created page with "{{Infobox BSP |BSP_name = phyCORE-MPC5554 |Manufacturer = Freescale |image = PhyCORE.jpg |CPU_model = MPC5554, up to 132 MHz CPU speed |RAM = 64 kByte SRAM..."

TBR/BSP/Phycore_mpc5554

@@ +1 @@
+= Phycore mpc5554 =
+
+
+{{Infobox BSP
+|BSP_name     = phyCORE-MPC5554
+|Manufacturer = Freescale
+|image        = PhyCORE.jpg
+|CPU_model    = MPC5554, up to 132 MHz CPU speed
+|RAM          = 64 kByte SRAM; 32 kByte capable of battery buffering
+|Architecture = PowerPC
+|Board_URL    = http://www.phytec.com/products/som/PowerPC/phyCORE-MPC5554.html
+
+}}
+The phyCORE-MPC5554 belongs to PHYTEC’s phyCORE Single Board Computer module family. The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core  elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and  embedding in peripheral hardware developments. = Overview =
+
+The Freescale MPC5554 PowerPC microcontroller embodies the continued development of the successful MPC500 family. This device expands upon the functions and features of the MPC565 by offering enhanced eTPU and eQADC, as well as more than doubling the clock frequency to 132MHz and introducing an Instruction Cache while requiring a low 1V5 core power supply.  5V, 3V3 and 1V5 core supply voltages are generated on-board.  The MPC5554 offers system performance of up to five times higher than its MPC500 predecessors. It offers 2 MB on-chip Flash memory, enhanced timer systems, and a peripheral set tailored for automotive and industrial applications.  Based on the PowerPC architecture and instruction set, the MPC5554 32-bit embedded controller has been designed for real-time control applications such as automotive powertrain systems.
+
+
+
+As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference) problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package. The increased pin package allows dedication of approximately 20 % of all pin header connectors on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments.
+
+
+phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0402-packaged SMD and laser-drilled Microvias components are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration 
+into their own design. 
+
+
+The phyCORE-MPC5554 is a subminiature (84 x 57 mm) insert-ready Single Board Computer populated with Freescale's PowerPC MPC5554 microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density (0.635 mm) Molex pin header connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a target application= System Start-Up Configuration =
+
+The phyCORE-MPC5554 supports four  different software start-up 
+modes: 
+ *  Internal Flash Memory 
+ *  External Memory controlled by /CS0 
+ *  SCI UART 
+ *  FlexCAN = Internal/External Memory Boot = 
+The decision which mode is used  after /RESET goes from active to 
+inactive state is defined by the external signal /RSTCFG (X2C9). The 
+default state of this signal is high configured by an on-board pull-up 
+resistor to VDD3V3. 
+= System Memory =
+
+
+The system memory consist of  internal MPC5554 Flash memory, external standard Flash memory, Synchronous Burst SRAM
+and a small non-volatile memory device: 
+ *  2 MByte internal MPC5554 Flash (read while write functionality) 
+ *  2 MByte to 8 MByte asynchronous standard Flash-EEPROM, 32-bit access 
+ *  1 MByte to 16 MByte flow-through synchronous Burst SRAM, 32-bit access, 0 wait states, 2-1-1-1 burst mode 
+ *  I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C FRAM, I2C SRAM) 
+The external Flash and sync. SRAM are connected to the MPC5554 32-bit data bus. The Flash is controlled by /CS0 for boot operation. The Synchronous Burst SRAM is controlled by /CS1 and supports the special synchronous burst modes that enables maximum data transfer rates. 
+Communication with the small non-volatile memory device (EPROM, 
+FRAM or SRAM) is established over the I2C bus. This memory device can be used for storage of system parameters or configuration data
+= References =
+
+http://www.phytec.eu/europe/products/product-details/p/phycore-mpc5554-2.html
+
+http://www.phytec.com/products/som/PowerPC/phyCORE-MPC5554.html
+
+http://www.phytec.com/pdf/manuals/L-484e.pdf