Changes between Version 42 and Version 43 of TBR/BSP/Nios2_iss

Timestamp:

11/13/18 22:33:43 (6 years ago)

Author:

Marçal Comajoan Cara

Comment:

change image links to attachments and improve format

TBR/BSP/Nios2_iss

@@ -2 +2 @@
 
 
-== Infobox BSP ==
-||'''BSP_name'''        ||Nios2 iss||     
-||'''Manufacturer'''    ||Altera||
-||'''image'''           ||Nios2.jpg||
-||'''Board_URL'''       ||[http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf]||
-||'''NVRAM'''           ||N/A|| 
-||'''Architecture'''    ||N/A|| 
-||'''Simulator'''       ||Instruction Set Simulator||
-||'''RAM'''             ||DDR SDRAM memory||
-||'''NVMEM'''           ||CFI Flash memory||
-||'''CPU_model'''       ||Nios II 100MHz||
-||'''Serial'''          ||N/A|| 
-||'''Other'''           ||N/A|| 
+= Infobox BSP
+||=BSP_name        ||Nios2 iss||     
+||=Manufacturer    ||Altera||
+||=Image           ||Nios2.jpg||
+||=Board_URL       ||[http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf]||
+||=NVRAM           ||N/A|| 
+||=Architecture    ||N/A|| 
+||=Simulator       ||Instruction Set Simulator||
+||=RAM             ||DDR SDRAM memory||
+||=NVMEM           ||CFI Flash memory||
+||=CPU_model       ||Nios II 100MHz||
+||=Serial          ||N/A|| 
+||=Other           ||N/A|| 
 
 = Overview =
-
-= Nios2 iss =
 
 The microprocessor design is based on the Nios II/f core and provides a typical mix of peripherals, memories, and a video pipeline. The design provides an interface to each hardware component on the Altera Nios II Embedded Evaluation Kit, Cyclone III Edition, such as DDR SDRAM, LEDs, RS-232 connector, Ethernet MAC/10/100 PHY, and 800 × 480 pixel LCD. The video pipeline provides high bandwidth memory access that allows for flicker-free display on the color LCD.
@@ -108 +106 @@
 = Block diagram =
 
-[[Image(https://devel.rtems.org/old_images/Niosblock.png)]]
+[[Image(Niosblock.png)]]
 
 = References =