wiki:TBR/BSP/Nios2_iss

Nios2 iss

Infobox BSP

BSP_name Nios2 iss
Manufacturer Altera
Image Nios2.jpg
Board_URL http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf
NVRAM N/A
Architecture N/A
Simulator Instruction Set Simulator
RAM DDR SDRAM memory
NVMEM CFI Flash memory
CPU_model Nios II 100MHz
Serial N/A
Other N/A

Overview

The microprocessor design is based on the Nios II/f core and provides a typical mix of peripherals, memories, and a video pipeline. The design provides an interface to each hardware component on the Altera Nios II Embedded Evaluation Kit, Cyclone III Edition, such as DDR SDRAM, LEDs, RS-232 connector, Ethernet MAC/10/100 PHY, and 800 × 480 pixel LCD. The video pipeline provides high bandwidth memory access that allows for flicker-free display on the color LCD.

Processor

The Nios II processor runs at a frequency of 100 MHz and is connected to high performance DDR SDRAM memory, on-chip descriptor memory, and CFI flash memory. Clock crossing bridges are required between the Nios II processor and the DDR SDRAM memory and slow peripherals components because these components run in different clock regions. A pipeline bridge between the Nios II processor and the flash tri-state bridge to external flash component ensures system fMAX is not affected and that every master sees every slave at the same address. The DDR SDRAM memory runs at 133 MHz. The ddr_sdram memory controller runs at half rate at local interface with a 64-bit data width, connected to a 32-bit width Nios II data bus and a 64-bit width SG-DMA through clock crossing bridges.

Processor type: Fast (Nios /f)

  • 32-bit RISC
  • Instruction cache
  • Data cache
  • Branch prediction
  • Hardware multiply
  • Hardware divide
  • Barrel shifter
  • Dynamic branch prediction

Nominal metrics:

  • Nominal performance at 100 MHz: Up to 113 DMIPS
  • Nominal logic usage: 1400-1800 LEs
  • Nominal memory usage: Three M9K + Cache

Reset vector:

  • Memory: ext_flash
  • Offset: 0x0
  • Physical address: 0x04000000

Exception vector:

  • Memory: ssram
  • Offset: 0x20
  • Physical address: 0x05000020

I/O

The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. The following table shows the LED PIO parameters and corresponding parameter values.

Parameter Value
Name led_pio
Width (1-32 bits) 2
Direction Output ports only
Output port reset value 0x0

The following table shows the Button PIO parameters and corresponding parameter values.

Parameter Value
Name button_pio
Width (1-32 bits) 4
Direction Input ports only
Input options Edge capture register: synchronous capture, rising edge
Interrupt generated: edge based

Memory

CFI Flash Interface

The Altera CFI-compliant flash memory controller core controls an external flash device (Intel). This flash device stores both application program code and FPGA configuration data. With 16 MByte capacity, it is possible to store multiple configuration images in flash memory and configure the FPGA with one of the images.

Parameter Value
Name ext_flash
Address width 23
Data width 16
Flash capacity 16 MByte
Timing settings Setup: 25 ns
Wait: 100 ns
Hold: 20 ns

DDR SDRAM Memory Controller

The Altera DDR SDRAM High Performance MegaCore function is used to interface to a PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.

Parameter Value
Name ddr_sdram
PLL reference clock frequency 50 MHz
Memory clock frequency 133 MHz
Local interface clock frequency 66.5 MHz
Local interface width 64 bits

SD/MMC SPI

The SD/MMC SPI core connects to standard multimedia card (MMC) and secure digital (SD) flash based memory devices. The MMC and SD card are universal low cost data storage memories. The SD/MMC SPI core is available from El Camino GmbH in encrypted format, for evaluation purposes. The SD/MMC SPI core also comes with low-level driver routines to access the MMC and SD devices. Features:

  • 2,400 KBytes per second read and 2,400 KBytes per second write performance
  • Supports MMC and SD in SPI mode
  • Variable data rate up to 25 Mbps (SD only) and 20 Mbps (SD/MMC)
  • Hardware assisted CRC calculation
  • Low level drivers included
Parameter Value
Name el_camino_sd_card_controller
Avalon bus clock frequency 60 MHz
SPI clock frequency 20 MHz

Block diagram

References

Last modified on Nov 13, 2018 at 10:33:43 PM Last modified on Nov 13, 2018, 10:33:43 PM

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