Changes between Version 41 and Version 42 of TBR/BSP/Nios2_iss


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Timestamp:
Nov 13, 2018, 10:29:49 PM (7 months ago)
Author:
Sal
Comment:

convert images to tables

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  • TBR/BSP/Nios2_iss

    v41 v42  
    4949= I/O =
    5050
    51 The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. Table 7 shows the LED PIO parameters and corresponding parameter values.
     51The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. The following table shows the LED PIO parameters and corresponding parameter values.
    5252
    53 [[Image(https://devel.rtems.org/old_images/Io1.png)]]
     53||= Parameter =||= Value =||
     54|| Name || ''led_pio'' ||
     55|| Width (1-32 bits) || 2 ||
     56|| Direction || Output ports only ||
     57|| Output port reset value || 0x0 ||
    5458
    55 Table 8 shows the Button PIO parameters and corresponding parameter values.
     59The following table shows the Button PIO parameters and corresponding parameter values.
    5660
    57 [[Image(https://devel.rtems.org/old_images/Io2.png)]]
     61||= Parameter =||= Value =||
     62|| Name || ''button_pio'' ||
     63|| Width (1-32 bits) || 4 ||
     64|| Direction || Input ports only ||
     65|| Input options || Edge capture register: synchronous capture, rising edge \\ Interrupt generated: edge based ||
     66
    5867= Memory =
    5968
     
    6372The Altera CFI-compliant flash memory controller core controls an external flash device (Intel). This flash device stores both application program code and FPGA configuration data. With 16 MByte capacity, it is possible to store multiple configuration images in flash memory and configure the FPGA with one of the images.
    6473
    65 [[Image(https://devel.rtems.org/old_images/Cfi.png)]]
     74
     75||= Parameter =||= Value =||
     76|| Name || ''ext_flash'' ||
     77|| Address width || 23 ||
     78|| Data width || 16 ||
     79|| Flash capacity || 16 MByte ||
     80|| Timing settings || Setup: 25 ns \\ Wait: 100 ns \\ Hold: 20 ns ||
    6681
    6782'''DDR SDRAM Memory Controller'''
     
    6984The Altera DDR SDRAM High Performance !MegaCore function is used to interface to a !PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The !MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.
    7085
    71 [[Image(https://devel.rtems.org/old_images/sdram1.png)]]
     86||= Parameter =||= Value =||
     87|| Name || ''ddr_sdram'' ||
     88|| PLL reference clock frequency || 50 MHz ||
     89|| Memory clock frequency || 133 MHz ||
     90|| Local interface clock frequency || 66.5 MHz ||
     91|| Local interface width || 64 bits ||
    7292
    7393'''SD/MMC SPI'''
     
    81101 *  Low level drivers included
    82102
    83 [[Image(Spi1.png)]]
     103||= Parameter =||= Value =||
     104|| Name || ''el_camino_sd_card_controller'' ||
     105|| Avalon bus clock frequency || 60 MHz ||
     106|| SPI clock frequency || 20 MHz ||
    84107
    85108= Block diagram =