Changes between Version 41 and Version 42 of TBR/BSP/Nios2_iss

Timestamp:

11/13/18 22:29:49 (6 years ago)

Author:

Marçal Comajoan Cara

Comment:

convert images to tables

TBR/BSP/Nios2_iss

@@ -49 +49 @@
 = I/O =
 
-The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. Table 7 shows the LED PIO parameters and corresponding parameter values.
+The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. The following table shows the LED PIO parameters and corresponding parameter values.
 
-[[Image(https://devel.rtems.org/old_images/Io1.png)]]
+||= Parameter =||= Value =||
+|| Name || ''led_pio'' ||
+|| Width (1-32 bits) || 2 ||
+|| Direction || Output ports only ||
+|| Output port reset value || 0x0 ||
 
-Table 8 shows the Button PIO parameters and corresponding parameter values.
+The following table shows the Button PIO parameters and corresponding parameter values.
 
-[[Image(https://devel.rtems.org/old_images/Io2.png)]]
+||= Parameter =||= Value =||
+|| Name || ''button_pio'' ||
+|| Width (1-32 bits) || 4 ||
+|| Direction || Input ports only ||
+|| Input options || Edge capture register: synchronous capture, rising edge \\ Interrupt generated: edge based ||
+
 = Memory =
 
@@ -63 +72 @@
 The Altera CFI-compliant flash memory controller core controls an external flash device (Intel). This flash device stores both application program code and FPGA configuration data. With 16 MByte capacity, it is possible to store multiple configuration images in flash memory and configure the FPGA with one of the images.
 
-[[Image(https://devel.rtems.org/old_images/Cfi.png)]]
+
+||= Parameter =||= Value =||
+|| Name || ''ext_flash'' ||
+|| Address width || 23 ||
+|| Data width || 16 ||
+|| Flash capacity || 16 MByte ||
+|| Timing settings || Setup: 25 ns \\ Wait: 100 ns \\ Hold: 20 ns ||
 
 '''DDR SDRAM Memory Controller'''
@@ -69 +84 @@
 The Altera DDR SDRAM High Performance !MegaCore function is used to interface to a !PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The !MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.
 
-[[Image(https://devel.rtems.org/old_images/sdram1.png)]]
+||= Parameter =||= Value =||
+|| Name || ''ddr_sdram'' ||
+|| PLL reference clock frequency || 50 MHz ||
+|| Memory clock frequency || 133 MHz ||
+|| Local interface clock frequency || 66.5 MHz ||
+|| Local interface width || 64 bits ||
 
 '''SD/MMC SPI'''
@@ -81 +101 @@
  *  Low level drivers included
 
-[[Image(Spi1.png)]]
+||= Parameter =||= Value =||
+|| Name || ''el_camino_sd_card_controller'' ||
+|| Avalon bus clock frequency || 60 MHz ||
+|| SPI clock frequency || 20 MHz ||
 
 = Block diagram =