Changes between Version 39 and Version 40 of TBR/BSP/Nios2_iss

Timestamp:

11/13/18 20:32:22 (6 years ago)

Author:

Marçal Comajoan Cara

Comment:

--

TBR/BSP/Nios2_iss

@@ -67 +67 @@
 '''DDR SDRAM Memory Controller'''
 
-The Altera DDR SDRAM High Performance MegaCore function is used to interface to a PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.
+The Altera DDR SDRAM High Performance !MegaCore function is used to interface to a !PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The !MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.
 
 [[Image(https://devel.rtems.org/old_images/sdram1.png)]]