BSP Infobox

ManufacturerHitachi Semiconductor
Architecture32-bit RISC architecture
Operating Frequency80 MHz
OtherOriginal Hitachi architecture 32-bit internal data paths Five-stage pipeline


The SH2 was first manufactured in October 1993. The die size is 7.59mm by 7.44mm with an .8 micron die process. For comparison, modern CPUs are measured in nanometers. One nanometer is 1/1000 the size of one micron. The CPU chip size is 5.45mm².The SH-2 is a 32-bit RISC architecture, it has 16 general purpose registers, which makes it well suited for programs written in C[citation needed].It has a 16-bit fixed length instructions for high code density, features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.The SH-2 has a cache on all ROM-less devices.It also provides a vector-base-register, global-base-register and a procedure register.Today the SH-2 family stretches from 32k of on board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.The Hitachi SH2 processor is a custom-built, reduced instruction set computer architecture that belongs to the "Super-H" series. It was developed for embedded systems, such as motion-controlled robots, automobile engine control units and most notably, for the "Sega Saturn" gaming console. The main difference between the SH2 and the SH1 is that the SH2 has a cache.


This chip directly supports the popular memory interface types, such as SDRAM, DRAM and Masked ROM. It includes a 32-bit fixed point multiplier and division unit for 3D calculations. The SH2 can be configured to support a dual-processor.

Power Consumption

SH2 processors consume 400MHz at 5 volts. The operating voltage range can be between 2.7 volts to 5.5 volts. The clock frequency is 28.7MHz for a CPU throughput of 25 million instructions per second.


This processor has a 32-bit architecture, with 16 fixed length instructions and 16 general purpose registers, making it ideal for "C" language programming. The earliest SH2 had 4 kilobytes of cache for code pre-fetching. More advanced processors in the family had up to 32KB.


<br />

  • Architecture:

•Original Hitachi architecture <br /> •32-bit internal data paths

<br />

  • General-register machine:

•Sixteen 32-bit general registers <br /> •Three 32-bit control registers <br /> •Four 32-bit system registers

<br />

  • Instruction set Instruction length:

•16-bit fixed length for improved code efficiency <br /> •Load-store architecture (basic arithmetic and logic operations areexecuted between registers) <br /> •Delayed branch system used for reduced pipeline disruption <br /> •Instruction set optimized for C language

<br />

  • Instruction execution time:

•One instruction/cycle for basic instructions

<br />

  • Address space:

•Architecture makes 4 Gbytes available

<br />

  • On-chip multiplier(SH-2 CPU):

•Multiplication operations executed in 1 to 2 cycles (16 bits × 16 bits? 32 bits) or 2 to 4 cycles (32 bits × 32 bits ? 64 bits), and multiplication/accumulation operations executed in 3/(2)*cycles (16bits × 16 bits + 64 bits ? 64 bits) or 3/(2 to 4)* cycles (32 bits × 32bits + 64 bits ? 64 bits)

<br />

  • Pipeline:

•Five-stage pipeline

<br />

  • Processing states:

•Reset state <br /> •Exception processing state <br /> •Program execution state <br /> •Power-down state <br /> •Bus release state

<br />

  • Power-down states:

•Sleep mode <br /> •Standby mode <br /> Note:The normal minimum number of execution cycles (The number in parentheses in the mumber in contention with preceding/following instructions).


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Last modified on Nov 7, 2018 at 4:34:48 AM Last modified on Nov 7, 2018, 4:34:48 AM