Changes between Version 1 and Version 2 of Developer/AtomicSupport

Timestamp:

04/05/13 11:53:56 (11 years ago)

Author:

WeiY

Comment:

Developer/AtomicSupport

@@ -4 +4 @@
 
 
-The following table summarizes the atomic support among the CPU architectures supported by the git development head.  The target CPU and branch number are used in constructing the target name for the GNU tools and RTEMS with the pattern CPU-rtemsBRANCH with the CVS head becoming the 4.9 branch.  For example, for the Coldfire CPUs, the '''Target CPU''' is m68k yielding a target name of m68k-rtems4.10 for the target name using RTEMS 4.10 series releases.
+The following table summarizes the atomic support among the CPU architectures supported by the git development head.  The RTEMS-SMP means whether the SMP mode is supported by the latest SMP. The atomic-hardware means whether the architecture has atomic hardware instruction support. 
 
 {| border="1" style="margin: 1em auto 1em auto;text-align: center;"
@@ -11 +11 @@
 |'''Architecture''' || '''Target CPU''' || '''RTEMS SMP''' || '''atomic-hardware''' || '''atomic-instruction''' || '''memory-ordering'''
 |-
-| X86 || i386 || yes || yes || cmpxchg || stronger
+| X86 || i386 || Yes || Yes || cmpxchg || Stronger
 |-
-| PowerPC || powerpc || no || yes || lwarx/stwcx || weaker
+| PowerPC || powerpc || No || Yes || lwarx/stwcx || Weaker
 |-
-| Texas Instruments C3x/C4x || tic4x || Yes || No || No || No || Yes || No
+| SPARC (V7-V8) || sparc || No || Yes || ldstub/swap || Stronger (TSO-mode)
+|-
+| SPARC V9 || sparc || No || Yes || ldstub/swap/cas || Stronger (TSO-mode)
+|-
+| MIPS || mips || No || Yes || ll/sc || Weaker
+|-
+| ARM || arm || No || Yes (V6 above) || ldstub/swap (V6 above) || Weaker
+|-
+| M68K || m68k || No || Yes || cad/cas32/tas || 
+|-
+| Blackfin || bfin || No || no || no || 
+|-
+| SH || sh || No || Yes ||  || 
 |-
 |}
+
+References:
+1. http://dsc.sun.com/solaris/articles/atomic_sparc/
+2. http://semipublic.comp-arch.net/wiki/Load-linked/store-conditional_%28LL/SC%29
+3. http://en.wikipedia.org/wiki/Memory_ordering
+4. http://www.sigma.me/2011/12/14/mips-llsc-instruction.html