#4202 assigned enhancement

Add BSP for ARM Fixed Virtual Platform with a Cortex-R52

Reported by: Sebastian Huber Owned by: Sebastian Huber
Priority: normal Milestone: 6.1
Component: arch/arm Version: 6
Severity: normal Keywords:
Cc: Blocked By:
Blocking:

Description


Change History (33)

comment:1 Changed on Dec 9, 2020 at 4:32:14 PM by Sebastian Huber <sebastian.huber@…>

In 9ce47a5/rtems:

bsps: Add SMP support to ARM GICv3

Update #4202.

comment:2 Changed on Dec 10, 2020 at 8:08:19 AM by Sebastian Huber <sebastian.huber@…>

In 9955487d/rtems:

arm: Support Armv8 in <rtems/score/arm.h>

Update #4202.

comment:3 Changed on Dec 10, 2020 at 8:08:22 AM by Sebastian Huber <sebastian.huber@…>

In e68827e/rtems:

arm/cache-cp15: Support Armv8

Update #4202.

comment:4 Changed on Dec 10, 2020 at 8:08:26 AM by Sebastian Huber <sebastian.huber@…>

In 5efa15b/rtems:

bsps/arm: Unify ARM Generic Timer options

Update #4202.

comment:5 Changed on Dec 10, 2020 at 8:08:29 AM by Sebastian Huber <sebastian.huber@…>

In bd7bef52/rtems:

bsps/arm: Support system level ARM Generic Timer

Update #4202.

comment:6 Changed on Dec 10, 2020 at 8:08:32 AM by Sebastian Huber <sebastian.huber@…>

In 617aeaf5/rtems:

bsps/arm: Move BSP_START_IN_HYP_SUPPORT option

Clarify documentation.

Update #4202.

comment:7 Changed on Dec 10, 2020 at 3:19:15 PM by Sebastian Huber <sebastian.huber@…>

In b6925e1/rtems:

bsps: Fix GICv3 arm_gic_trigger_sgi()

Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.

Update #4202.

comment:8 Changed on Dec 10, 2020 at 3:19:18 PM by Sebastian Huber <sebastian.huber@…>

In 105e520/rtems:

bsps: Remove ARM GIC SGI target filter

Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.

Update #4202.

comment:9 Changed on Dec 17, 2020 at 2:32:46 PM by Sebastian Huber <sebastian.huber@…>

In 747fb65/rtems:

bsps: Add GICv3 arm_gic_irq_processor_count()

Update #4202.

comment:10 Changed on Dec 17, 2020 at 2:32:50 PM by Sebastian Huber <sebastian.huber@…>

In b5aceef/rtems:

bsps: Remove gicvx_interrupt_dispatch()

Avoid one level of indirection.

Update #4202.

comment:11 Changed on Dec 17, 2020 at 2:32:53 PM by Sebastian Huber <sebastian.huber@…>

In a299c4fe/rtems:

arm: Optimize arm_interrupt_disable()

Update #4202.

comment:12 Changed on Dec 23, 2020 at 9:26:50 AM by Sebastian Huber <sebastian.huber@…>

In be5eee57/rtems:

libdebugger: Fix for Armv8-R

This architecture variant has no MMU.

Update #4202.

comment:13 Changed on Dec 23, 2020 at 9:26:54 AM by Sebastian Huber <sebastian.huber@…>

In 39ef7e5/rtems:

bsps: Fix includes

Update #4202.

comment:14 Changed on Dec 23, 2020 at 9:26:57 AM by Sebastian Huber <sebastian.huber@…>

In 6944cd10/rtems:

arm: Add header file for AArch32 System Registers

Update #4202.

comment:15 Changed on Dec 23, 2020 at 9:27:00 AM by Sebastian Huber <sebastian.huber@…>

In 854ea2b/rtems:

arm: Add support for Arm PMSAv8-32

Update #4202.

comment:16 Changed on Dec 23, 2020 at 9:27:03 AM by Sebastian Huber <sebastian.huber@…>

In 272534e/rtems:

bsps/arm: Set VBAR in start.S

Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.

Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().

Update #4202.

comment:17 Changed on Dec 23, 2020 at 9:27:07 AM by Sebastian Huber <sebastian.huber@…>

In 76a1a53/rtems:

bsps/arm: Invalidate branch predictors earlier

Make sure the branch predictors are invalidated before the first branch
is executed.

Update #4202.

comment:18 Changed on Dec 23, 2020 at 9:27:10 AM by Sebastian Huber <sebastian.huber@…>

In 46a3c04/rtems:

bsps/arm: Remove optional start hook arguments

The start hook arguments are not used by a BSP. Removing them avoids
the need for a stack during the very early system initialization.

Update #4202.

comment:19 Changed on Dec 23, 2020 at 9:27:13 AM by Sebastian Huber <sebastian.huber@…>

In b32fd227/rtems:

bsps/arm: Add arm-data-cache-loop-set-way.h

This makes it possible to reuse this loop.

Update #4202.

comment:20 Changed on Dec 23, 2020 at 9:27:17 AM by Sebastian Huber <sebastian.huber@…>

In e164df5e/rtems:

bsps/arm: Clear SCTLR[M, I, A, C] in start.S

Initialize the data and unified cache levels. Invalidate the
instruction cache levels.

Update #4202.

comment:21 Changed on Dec 23, 2020 at 9:27:20 AM by Sebastian Huber <sebastian.huber@…>

In 23d9223a/rtems:

bsps/arm: Invalidate TLB in start.S

Update #4202.

comment:22 Changed on Dec 23, 2020 at 9:27:23 AM by Sebastian Huber <sebastian.huber@…>

In 9f3a08e/rtems:

bsps: Use header file for GIC architecture support

This avoids a function call overhead in the interrupt dispatching.

Update #4202.

comment:23 Changed on Dec 23, 2020 at 9:27:27 AM by Sebastian Huber <sebastian.huber@…>

In 016bcb3/rtems:

bsps/arm: Rely on initialized vector table

The arm_cp15_set_exception_handler() is a complicated function which
should be avoided if possible.

Update #4202.

comment:24 Changed on Dec 23, 2020 at 9:27:30 AM by Sebastian Huber <sebastian.huber@…>

In 81c7f5be/rtems:

arm/fvp: New BSP

This BSP supports the Arm Fixed Virtual Platform. Only the Cortex-R52
processor configuration is supported by the BSP. It should be easy to
add support for other variants if needed.

Update #4202.

comment:25 Changed on Jan 4, 2021 at 5:12:11 AM by Sebastian Huber <sebastian.huber@…>

In 90342fe/rtems-tools:

tester: Add support for arm/fvp_cortex_r52 BSP

Update #4202.

comment:26 Changed on Jan 4, 2021 at 9:59:30 AM by Sebastian Huber <sebastian.huber@…>

In 1e9c608/rtems-source-builder:

6/7: Update to the latest rtems-tools

Update #4202.

comment:27 Changed on Jun 7, 2021 at 7:41:26 AM by Sebastian Huber <sebastian.huber@…>

In 2d1c494f/rtems:

arm/fvp: Remove unused GICv2 BSP option

Update #4202.

comment:28 Changed on Jun 7, 2021 at 7:41:29 AM by Sebastian Huber <sebastian.huber@…>

In 55ce66ca/rtems:

arm/fvp: Fix integer from pointer without a cast

Update #4202.

comment:29 Changed on Jun 16, 2021 at 3:49:05 PM by Sebastian Huber <sebastian.huber@…>

In f89a527/rtems:

arm: Fix parameter use in AARCH32_PMSA_MEM_ATTR()

Update #4202.

comment:30 Changed on Jun 29, 2021 at 12:59:30 PM by Sebastian Huber <sebastian.huber@…>

In 13b18d12/rtems:

arm: Disable alignment check in PMSA init

Disable the alignment check through SCTLR[A] in
_AArch32_PMSA_Initialize().

Update #4202.

comment:31 Changed on Jun 29, 2021 at 12:59:34 PM by Sebastian Huber <sebastian.huber@…>

In b357680/rtems:

arm: Fix AArch32 memory attribute defines

Update #4202.

comment:32 Changed on Jun 29, 2021 at 12:59:37 PM by Sebastian Huber <sebastian.huber@…>

In 9b84adb/rtems:

arm: Fix AARCH32_PMSA_ATTR_XN value

Update #4202.

comment:33 Changed on Jun 29, 2021 at 12:59:41 PM by Sebastian Huber <sebastian.huber@…>

In bb9a4b8/rtems:

arm: For AArch32 use non-shareable memory

The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.

Update #4202.

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