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Opened on 12/09/20 at 13:31:40

Closed on 09/09/22 at 05:41:43

Last modified on 09/22/22 at 05:55:24

#4202 closed enhancement (fixed)

Add BSP for ARM Fixed Virtual Platform with a Cortex-R52

Reported by: Sebastian Huber Owned by: Sebastian Huber
Priority: normal Milestone: 6.1
Component: arch/arm Version: 6
Severity: normal Keywords:
Cc: Blocked By:
Blocking:

Description


Change History (39)

comment:1 Changed on 12/09/20 at 16:32:14 by Sebastian Huber <sebastian.huber@…>

In [changeset:"9ce47a52a49cadd3505576e0462fb908f40be0b7/rtems" 9ce47a5/rtems]:

bsps: Add SMP support to ARM GICv3

Update #4202.

comment:2 Changed on 12/10/20 at 08:08:19 by Sebastian Huber <sebastian.huber@…>

In [changeset:"9955487de6b92a08f932c8e9ea3a8a130a2ae040/rtems" 9955487d/rtems]:

arm: Support Armv8 in <rtems/score/arm.h>

Update #4202.

comment:3 Changed on 12/10/20 at 08:08:22 by Sebastian Huber <sebastian.huber@…>

In [changeset:"e68827e1d9453ca47f95bafe0aac45fc4f7b8e6d/rtems" e68827e/rtems]:

arm/cache-cp15: Support Armv8

Update #4202.

comment:4 Changed on 12/10/20 at 08:08:26 by Sebastian Huber <sebastian.huber@…>

In [changeset:"5efa15b49d47ace494410e423fc69213d9c2a4e9/rtems" 5efa15b/rtems]:

bsps/arm: Unify ARM Generic Timer options

Update #4202.

comment:5 Changed on 12/10/20 at 08:08:29 by Sebastian Huber <sebastian.huber@…>

In [changeset:"bd7bef528db094914cefef040ddca6c5a0e963d1/rtems" bd7bef52/rtems]:

bsps/arm: Support system level ARM Generic Timer

Update #4202.

comment:6 Changed on 12/10/20 at 08:08:32 by Sebastian Huber <sebastian.huber@…>

In [changeset:"617aeaf572777886fd5dd11b1d8a283fd9865201/rtems" 617aeaf5/rtems]:

bsps/arm: Move BSP_START_IN_HYP_SUPPORT option

Clarify documentation.

Update #4202.

comment:7 Changed on 12/10/20 at 15:19:15 by Sebastian Huber <sebastian.huber@…>

In [changeset:"b6925e10c8a7990ef9d9649e0f13ac0cbdd41071/rtems" b6925e1/rtems]:

bsps: Fix GICv3 arm_gic_trigger_sgi()

Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.

Update #4202.

comment:8 Changed on 12/10/20 at 15:19:18 by Sebastian Huber <sebastian.huber@…>

In [changeset:"105e52032e524873924ddec0167535a33f8cd9f7/rtems" 105e520/rtems]:

bsps: Remove ARM GIC SGI target filter

Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.

Update #4202.

comment:9 Changed on 12/17/20 at 14:32:46 by Sebastian Huber <sebastian.huber@…>

In [changeset:"747fb65c6e5921c39c324c6e86ab2f2d87b47ee0/rtems" 747fb65/rtems]:

bsps: Add GICv3 arm_gic_irq_processor_count()

Update #4202.

comment:10 Changed on 12/17/20 at 14:32:50 by Sebastian Huber <sebastian.huber@…>

In [changeset:"b5aceef5d921de3d146b45c20f6f8aa7e9413717/rtems" b5aceef/rtems]:

bsps: Remove gicvx_interrupt_dispatch()

Avoid one level of indirection.

Update #4202.

comment:11 Changed on 12/17/20 at 14:32:53 by Sebastian Huber <sebastian.huber@…>

In [changeset:"a299c4feef70318c5098cb1d15557b37ac253d17/rtems" a299c4fe/rtems]:

arm: Optimize arm_interrupt_disable()

Update #4202.

comment:12 Changed on 12/23/20 at 09:26:50 by Sebastian Huber <sebastian.huber@…>

In [changeset:"be5eee575b166f8f351cec0a1e988a6bc8cbd2bb/rtems" be5eee57/rtems]:

libdebugger: Fix for Armv8-R

This architecture variant has no MMU.

Update #4202.

comment:13 Changed on 12/23/20 at 09:26:54 by Sebastian Huber <sebastian.huber@…>

In [changeset:"39ef7e549669c657b21128ad2e10bc65e459c019/rtems" 39ef7e5/rtems]:

bsps: Fix includes

Update #4202.

comment:14 Changed on 12/23/20 at 09:26:57 by Sebastian Huber <sebastian.huber@…>

In [changeset:"6944cd10e6bdc450d66ab245bf0620979fba8f71/rtems" 6944cd10/rtems]:

arm: Add header file for AArch32 System Registers

Update #4202.

comment:15 Changed on 12/23/20 at 09:27:00 by Sebastian Huber <sebastian.huber@…>

In [changeset:"854ea2b4d8a32753da9afe8770be191cd0b4ade8/rtems" 854ea2b/rtems]:

arm: Add support for Arm PMSAv8-32

Update #4202.

comment:16 Changed on 12/23/20 at 09:27:03 by Sebastian Huber <sebastian.huber@…>

In [changeset:"272534eb725f2486b7a32b39d998202a101bd36e/rtems" 272534e/rtems]:

bsps/arm: Set VBAR in start.S

Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.

Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().

Update #4202.

comment:17 Changed on 12/23/20 at 09:27:07 by Sebastian Huber <sebastian.huber@…>

In [changeset:"76a1a5378031e56d29d16c713aee73c6747c3e61/rtems" 76a1a53/rtems]:

bsps/arm: Invalidate branch predictors earlier

Make sure the branch predictors are invalidated before the first branch
is executed.

Update #4202.

comment:18 Changed on 12/23/20 at 09:27:10 by Sebastian Huber <sebastian.huber@…>

In [changeset:"46a3c0446f6a18ca1fa9e6995504bc7291d66495/rtems" 46a3c04/rtems]:

bsps/arm: Remove optional start hook arguments

The start hook arguments are not used by a BSP. Removing them avoids
the need for a stack during the very early system initialization.

Update #4202.

comment:19 Changed on 12/23/20 at 09:27:13 by Sebastian Huber <sebastian.huber@…>

In [changeset:"b32fd22732ea9344bd7573c767573a3ce148c3f7/rtems" b32fd227/rtems]:

bsps/arm: Add arm-data-cache-loop-set-way.h

This makes it possible to reuse this loop.

Update #4202.

comment:20 Changed on 12/23/20 at 09:27:17 by Sebastian Huber <sebastian.huber@…>

In [changeset:"e164df5e33608576443b4cd5923a9046358ee773/rtems" e164df5e/rtems]:

bsps/arm: Clear SCTLR[M, I, A, C] in start.S

Initialize the data and unified cache levels. Invalidate the
instruction cache levels.

Update #4202.

comment:21 Changed on 12/23/20 at 09:27:20 by Sebastian Huber <sebastian.huber@…>

In [changeset:"23d9223ad3b67156b99d828457d0ebd74687cf71/rtems" 23d9223a/rtems]:

bsps/arm: Invalidate TLB in start.S

Update #4202.

comment:22 Changed on 12/23/20 at 09:27:23 by Sebastian Huber <sebastian.huber@…>

In [changeset:"9f3a08ef2de99714d679aecf6b1ecb4e11869424/rtems" 9f3a08e/rtems]:

bsps: Use header file for GIC architecture support

This avoids a function call overhead in the interrupt dispatching.

Update #4202.

comment:23 Changed on 12/23/20 at 09:27:27 by Sebastian Huber <sebastian.huber@…>

In [changeset:"016bcb3f9d82a0c02aab87326ce94bee0365a956/rtems" 016bcb3/rtems]:

bsps/arm: Rely on initialized vector table

The arm_cp15_set_exception_handler() is a complicated function which
should be avoided if possible.

Update #4202.

comment:24 Changed on 12/23/20 at 09:27:30 by Sebastian Huber <sebastian.huber@…>

In [changeset:"81c7f5be92803f96c39b5325006071771709125b/rtems" 81c7f5be/rtems]:

arm/fvp: New BSP

This BSP supports the Arm Fixed Virtual Platform. Only the Cortex-R52
processor configuration is supported by the BSP. It should be easy to
add support for other variants if needed.

Update #4202.

comment:25 Changed on 01/04/21 at 05:12:11 by Sebastian Huber <sebastian.huber@…>

In [changeset:"90342feb4dd63d188ce945adfb0a7694a42a65cd/rtems-tools" 90342fe/rtems-tools]:

tester: Add support for arm/fvp_cortex_r52 BSP

Update #4202.

comment:26 Changed on 01/04/21 at 09:59:30 by Sebastian Huber <sebastian.huber@…>

In [changeset:"1e9c608cb2fb27f4a4fd6c7f2cb4c1c1ce42cf62/rtems-source-builder" 1e9c608/rtems-source-builder]:

6/7: Update to the latest rtems-tools

Update #4202.

comment:27 Changed on 06/07/21 at 07:41:26 by Sebastian Huber <sebastian.huber@…>

In [changeset:"2d1c494fa86904544e4faa259289873a828b6a89/rtems" 2d1c494f/rtems]:

arm/fvp: Remove unused GICv2 BSP option

Update #4202.

comment:28 Changed on 06/07/21 at 07:41:29 by Sebastian Huber <sebastian.huber@…>

In [changeset:"55ce66ca7302cad0175fb6dc61df361659800b3e/rtems" 55ce66ca/rtems]:

arm/fvp: Fix integer from pointer without a cast

Update #4202.

comment:29 Changed on 06/16/21 at 15:49:05 by Sebastian Huber <sebastian.huber@…>

In [changeset:"f89a527336f12202b16d2534ea6a401703c97e9f/rtems" f89a527/rtems]:

arm: Fix parameter use in AARCH32_PMSA_MEM_ATTR()

Update #4202.

comment:30 Changed on 06/29/21 at 12:59:30 by Sebastian Huber <sebastian.huber@…>

In [changeset:"13b18d129e8f8ee92360ab5f27f1e71a3ec5016c/rtems" 13b18d12/rtems]:

arm: Disable alignment check in PMSA init

Disable the alignment check through SCTLR[A] in
_AArch32_PMSA_Initialize().

Update #4202.

comment:31 Changed on 06/29/21 at 12:59:34 by Sebastian Huber <sebastian.huber@…>

In [changeset:"b35768002624a2e7c075da53a8f4aacc7e1f21bf/rtems" b357680/rtems]:

arm: Fix AArch32 memory attribute defines

Update #4202.

comment:32 Changed on 06/29/21 at 12:59:37 by Sebastian Huber <sebastian.huber@…>

In [changeset:"9b84adb4aa7bfbd39cf8417863eae559426bfedb/rtems" 9b84adb/rtems]:

arm: Fix AARCH32_PMSA_ATTR_XN value

Update #4202.

comment:33 Changed on 06/29/21 at 12:59:41 by Sebastian Huber <sebastian.huber@…>

In [changeset:"bb9a4b816b7efaab4e1e45e4c1ea1d81f6c8a21e/rtems" bb9a4b8/rtems]:

arm: For AArch32 use non-shareable memory

The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.

Update #4202.

comment:34 Changed on 11/30/21 at 07:11:55 by Sebastian Huber <sebastian.huber@…>

In [changeset:"7fec89e24d5c5874599f4caacfdba43d42f25f7a/rtems" 7fec89e2/rtems]:

arm: Fix AARCH32_PMSA_DATA_READ_WRITE_CACHED

Fix definition of AARCH32_PMSA_DATA_READ_WRITE_CACHED. Since
AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO is zero, this fix is only cosmetic.

Update #4202.

comment:35 Changed on 11/30/21 at 07:11:59 by Sebastian Huber <sebastian.huber@…>

In [changeset:"73305a1044bcf7289bbfa8cebc925f06972f44cb/rtems" 73305a1/rtems]:

arm: Add AARCH32_PMSA_DATA_READ_WRITE_DEFAULT

Add default memory attributes for read-write data. The actual
attributes depend on the RTEMS_SMP build option.

Update #4202.

comment:36 Changed on 06/08/22 at 07:04:47 by Sebastian Huber <sebastian.huber@…>

In [changeset:"0b9497a6dd1cb89e9b8100572554d31598481f9f/rtems" 0b9497a/rtems]:

arm: Fix PMSA region mapping with 0x0 end address

A section may span up to the end of the address range. In this case the
end address is zero. Use the base address to check if a region should
be before another region.

Update #4202.

comment:37 Changed on 06/08/22 at 07:04:49 by Sebastian Huber <sebastian.huber@…>

In [changeset:"c93f0f01e5a260df008b568b74ca8bb7677e1bf5/rtems" c93f0f01/rtems]:

arm: Fix PMSA regions for contiguous sections

Sections with identical attributes may be contiguous with a respective
begin and end address which is not on a minimum region boundary. The
begin address is aligned down to the region base address. The end
address is aligned up to the region end address. Account for this in
the check for contiguous sections.

Update #4202.

comment:38 Changed on 09/09/22 at 05:41:43 by Sebastian Huber <sebastian.huber@…>

Resolution: → fixed
Status: assigned → closed

In [changeset:"13be9a2b282e6fd690512d4d75b5767fc69bbdb3/rtems-docs" 13be9a2/rtems-docs]:

user: Document arm/fvp BSP

Close #4202.

comment:39 Changed on 09/22/22 at 05:55:24 by Sebastian Huber <sebastian.huber@…>

In [changeset:"f6e7c627059e22da2f5ffb7853ef73b1200a1fa9/rtems" f6e7c627/rtems]:

bsps/arm: Mark functions in start.S

Add the function type to _start() and bsp_start_hook_0_done() so that
the linker can generate ARM/Thumb interworking code.

Update #4202.

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