#2472 closed defect (fixed)

Wrong value in PSR register after task switch on SPARC

Reported by: daniel.cederman Owned by: Daniel Cederman <cederman@…>
Priority: normal Milestone: 4.11
Component: arch/sparc Version: 4.11
Severity: critical Keywords:
Cc: Blocked By:
Blocking:

Description

The task switching code does not update the PSR if the heir changes during the switch (which happens if the original heir gets scheduled on another CPU). This can only happen with the SMP version of the code.

This can cause the FPU to be disabled and cause instructions that depends on condition codes to behave wrongly.

It can be solved by updating the PSR after the heir task has been acquired, instead of before.

Change History (2)

comment:1 Changed on Nov 17, 2015 at 7:59:53 AM by Daniel Cederman <cederman@…>

Owner: set to Daniel Cederman <cederman@…>
Resolution: fixed
Status: newclosed

In 2d7aad73ea79fdfd80fa466233c7dbeceb98d43c/rtems:

sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.

With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.

In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.

Close #2472.

comment:2 Changed on Oct 10, 2017 at 6:22:51 AM by Sebastian Huber

Component: SMParch/sparc
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