Changeset 29313369 in rtems


Ignore:
Timestamp:
Apr 7, 2010, 6:45:59 AM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
665446c1
Parents:
08013e8
Message:

changes to support GW_LCFM

Location:
c/src/lib/libcpu/powerpc
Files:
15 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r08013e8 r29313369  
     12010-04-07      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * mpc55xx/edma/edma.c, mpc55xx/esci/esci.c, mpc55xx/include/irq.h,
     4        mpc55xx/include/reg-defs.h, mpc55xx/include/regs.h,
     5        mpc55xx/misc/copy.S, mpc55xx/misc/fmpll.S, mpc5xx/irq/irq_init.c,
     6        mpc5xx/vectors/vectors_init.c,
     7        new-exceptions/bspsupport/ppc_exc_address.c,
     8        new-exceptions/bspsupport/ppc_exc_categories.c,
     9        new-exceptions/bspsupport/ppc_exc_initialize.c,
     10        shared/include/cpuIdent.c, shared/include/cpuIdent.h: adapted for
     11        GW_LCFM support
     12
    1132010-03-27      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
    214
  • c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c

    r08013e8 r29313369  
    3232#include <rtems/status-checks.h>
    3333
    34 #define MPC55XX_EDMA_CHANNEL_NUMBER 64U
    35 
    36 #define MPC55XX_EDMA_INVALID_CHANNEL MPC55XX_EDMA_CHANNEL_NUMBER
    37 
    38 #define MPC55XX_EDMA_IS_CHANNEL_INVALID( i) ((unsigned) (i) >= MPC55XX_EDMA_CHANNEL_NUMBER)
    39 
    40 #define MPC55XX_EDMA_IS_CHANNEL_VALID( i) ((unsigned) (i) < MPC55XX_EDMA_CHANNEL_NUMBER)
     34#if   ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     35#define MPC55XX_EDMA_CHANNEL_COUNT 16U
     36#else /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517)) */
     37#define MPC55XX_EDMA_CHANNEL_COUNT 64U
     38#endif /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517)) */
     39
     40#define MPC55XX_EDMA_INVALID_CHANNEL MPC55XX_EDMA_CHANNEL_COUNT
     41
     42#define MPC55XX_EDMA_IS_CHANNEL_INVALID( i) ((unsigned) (i) >= MPC55XX_EDMA_CHANNEL_COUNT)
     43
     44#define MPC55XX_EDMA_IS_CHANNEL_VALID( i) ((unsigned) (i) < MPC55XX_EDMA_CHANNEL_COUNT)
    4145
    4246#define MPC55XX_EDMA_IRQ_PRIORITY MPC55XX_INTC_DEFAULT_PRIORITY
     
    7983                error_channels_update = 0;
    8084
    81                 for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) {
     85                for (i = 0; i < MPC55XX_EDMA_CHANNEL_COUNT; ++i) {
    8286                        uint64_t channel_flags = 0;
    8387                        unsigned minor_link = i;
     
    126130
    127131        /* Clear the error interrupt requests */
    128         for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) {
     132        for (i = 0; i < MPC55XX_EDMA_CHANNEL_COUNT; ++i) {
    129133                if (IS_FLAG_SET( error_channels, MPC55XX_EDMA_CHANNEL_FLAG( i))) {
    130134                        EDMA.CER.R = (uint8_t) i;
     
    171175
    172176        /* Clear TCDs */
    173         memset( (void *)&EDMA.TCD [0], 0, sizeof( EDMA.TCD));
     177        memset( (void *)&EDMA.TCD [0], 0,
     178                MPC55XX_EDMA_CHANNEL_COUNT * sizeof( EDMA.TCD[0]));
    174179
    175180        /* Error interrupt handlers */
     
    183188        );
    184189        RTEMS_CHECK_SC( sc, "install low error interrupt handler");
     190
     191#if defined(MPC55XX_IRQ_EDMA_ERROR_HIGH)
    185192        sc = mpc55xx_interrupt_handler_install(
    186193                MPC55XX_IRQ_EDMA_ERROR_HIGH,
     
    192199        );
    193200        RTEMS_CHECK_SC( sc, "install high error interrupt handler");
     201#endif /* defined(MPC55XX_IRQ_EDMA_ERROR_HIGH) */
    194202
    195203        return RTEMS_SUCCESSFUL;
  • c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c

    r08013e8 r29313369  
    399399        }
    400400
    401         /* Set control registers */
    402         regs->CR1.R = cr1.R;
    403         regs->CR2.R = cr2.R;
    404 
    405401        /* Disable LIN */
    406402        regs->LCR.R = 0;
     403
     404        /* Set control registers */
     405        regs->CR2.R = cr2.R;
     406        regs->CR1.R = cr1.R;
    407407
    408408        return RTEMS_SUCCESSFUL;
  • c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h

    r08013e8 r29313369  
    3636#define MPC55XX_IRQ_MIN 0U
    3737#define MPC55XX_IRQ_MAX 328U
     38#define MPC55XX_IRQ_MIN 0U
     39#define MPC55XX_IRQ_MAX 328U
    3840#define MPC55XX_IRQ_BASE MPC55XX_IRQ_MIN
    3941#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
     
    4648#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
    4749
     50#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     51#else  /*((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
     52#endif /*((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
     53
     54#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     55
    4856/* eDMA interrupts */
    4957#define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
    50 #define MPC55XX_IRQ_EDMA_ERROR_HIGH 210U
     58#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
     59#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 26U
     60
     61#define MPC55XX_IRQ_EDMA_GET_CHANNEL( v) \
     62  ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
     63#define MPC55XX_IRQ_EDMA_GET_REQUEST( c) \
     64  ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
     65
     66/* SIU external interrupts */
     67#define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
     68#define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
     69#define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
     70#define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
     71#define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
     72
     73/* eMIOS interrupts */
     74#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 58U
     75#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 81U
     76#define MPC55XX_IRQ_EMIOS_GET_CHANNEL( v) \
     77  ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
     78#define MPC55XX_IRQ_EMIOS_GET_REQUEST( c) \
     79  ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
     80
     81#else  /*((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
     82
     83/* eDMA interrupts */
     84#define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
    5185#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
    5286#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 42U
     87
     88#define MPC55XX_IRQ_EDMA_ERROR_HIGH 210U
    5389#define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN 211U
    5490#define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MAX 242U
    55 #define MPC55XX_IRQ_EDMA_GET_CHANNEL( v) (((v) > MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX) ? ((v) + 32U - MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) : ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
    56 #define MPC55XX_IRQ_EDMA_GET_REQUEST( c) (((c) >= 32U) ? ((c) - 32U + MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) : ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
     91
     92#define MPC55XX_IRQ_EDMA_GET_CHANNEL( v) \
     93  (((v) > MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX)             \
     94   ? ((v) + 32U - MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN)    \
     95   : ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
     96#define MPC55XX_IRQ_EDMA_GET_REQUEST( c) \
     97  (((c) >= 32U)                                      \
     98   ? ((c) - 32U + MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
     99   : ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
    57100
    58101/* SIU external interrupts */
     
    68111#define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN 202U
    69112#define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MAX 209U
    70 #define MPC55XX_IRQ_EMIOS_GET_CHANNEL( v) (((v) > MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX) ? ((v) + 16U - MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) : ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
    71 #define MPC55XX_IRQ_EMIOS_GET_REQUEST( c) (((c) >= 16U) ? ((c) - 16U + MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) : ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
     113
     114#define MPC55XX_IRQ_EMIOS_GET_CHANNEL( v)             \
     115  (((v) > MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX)          \
     116   ? ((v) + 16U - MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
     117   : ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
     118
     119#define MPC55XX_IRQ_EMIOS_GET_REQUEST( c)             \
     120  (((c) >= 16U)                                       \
     121   ? ((c) - 16U + MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
     122   : ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
     123
     124#endif /*((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
    72125
    73126/* Checks */
    74 #define MPC55XX_IRQ_IS_VALID(v) ((v) >= MPC55XX_IRQ_MIN && (v) <= MPC55XX_IRQ_MAX)
    75 #define MPC55XX_IRQ_IS_SOFTWARE(v) ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
     127#define MPC55XX_IRQ_IS_VALID(v) \
     128  ((v) >= MPC55XX_IRQ_MIN &&    \
     129   (v) <= MPC55XX_IRQ_MAX)
     130#define MPC55XX_IRQ_IS_SOFTWARE(v) \
     131  ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
     132   (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
    76133
    77134/*
  • c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h

    r08013e8 r29313369  
    2222#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
    2323
     24#include <bspopts.h>
    2425/*
    2526 * Register addresses
     
    3233#define FLASH_BIUCR   0xFFFF801C
    3334#define SIU_ECCR      0xFFFE8984
     35#define SIU_SYSCLK    0xFFFE89A0
    3436#define SIU_SRCR      0xFFFE8010
     37
     38/*
     39 * Definitions for SIU_SYSCLK
     40 */
     41#define SIU_SYSCLK_SYSCLKSEL_MASK 0xC0000000
     42#define SIU_SYSCLK_SYSCLKSEL_IRC  0x00000000
     43#define SIU_SYSCLK_SYSCLKSEL_XOSC 0x40000000
     44#define SIU_SYSCLK_SYSCLKSEL_PLL  0x80000000
    3545
    3646#else /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
  • c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h

    r08013e8 r29313369  
    427427                  uint32_t:3;
    428428                uint32_t PS:1;
    429                   uint32_t:4;
     429                  uint32_t:3;
     430                uint32_t AD_MUX:1; /* only MPC551x */
    430431                uint32_t BL:1;
    431432                uint32_t WEBS:1;
     
    494495                  uint32_t:4;
    495496                uint32_t MDIS:1;
    496                   uint32_t:5;
     497                  uint32_t:3;
     498                uint32_t D16_32:1; /* only for MPC551x */
     499                uint32_t ADMUX:1;  /* only for MPC551x */
    497500                uint32_t DBM:1;
    498501            } B;
     
    44254428#define CAN_C     (*(volatile struct FLEXCAN2_tag *)  0xFFFC8000)
    44264429#define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFCC000)
    4427 #define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFD0000)
    4428 #define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFD4000)
     4430#define CAN_E     (*(volatile struct FLEXCAN2_tag *)  0xFFFD0000)
     4431#define CAN_F     (*(volatile struct FLEXCAN2_tag *)  0xFFFD4000)
    44294432
    44304433#define EMIOS     (*(volatile struct EMIOS_tag *)     0xFFFE4000)
  • c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S

    r08013e8 r29313369  
    2020
    2121#include <libcpu/powerpc-utility.h>
     22#include <bspopts.h>
    2223
    2324.section ".text"
    2425
     26/**
     27 * @fn int mpc55xx_copy_8( const void *src, void *dest, size_t n)
     28 *
     29 * @brief Copy @a n bytes from @a src to @a dest with 8 byte reads and writes.
     30 *
     31 * The memory areas should not overlap.  The addresses @a src and @a dest have
     32 * to be aligned on 8 byte boundaries.  The size @a n must be evenly divisible by 8.
     33 * The SPE operations @b evxor, @b evlddx and @b evstddx will be used.
     34 */
     35#if       ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))
     36GLOBAL_FUNCTION mpc55xx_copy_8
     37#endif /* ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517)) */
     38GLOBAL_FUNCTION mpc55xx_copy_4
     39        /* Loop counter = data size / 4 */
     40        srwi. r5, r5, 2
     41        beqlr
     42        mtctr r5
     43        xor   r5,r5,r5
     44copy_data4:
     45        lwzx  r6, r5, r3
     46        stwx  r6, r5, r4
     47        addi r5, r5, 4
     48        bdnz copy_data4
     49
     50        /* Return */
     51        blr
     52
     53#if  !((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))
    2554/**
    2655 * @fn int mpc55xx_copy_8( const void *src, void *dest, size_t n)
     
    4978        /* Return */
    5079        blr
    51 
     80#endif /*!((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))*/
     81
     82/**
     83 * @fn int mpc55xx_zero_4( void *dest, size_t n)
     84 *
     85 * @brief Zero all @a n bytes starting at @a dest with 4 byte writes.
     86 *
     87 * The address @a dest has to be aligned on 4 byte boundaries.  The size @a n
     88 * must be evenly divisible by 4.  No SPE operations are used.
     89 */
     90#if       ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))
     91GLOBAL_FUNCTION mpc55xx_zero_32
     92GLOBAL_FUNCTION mpc55xx_zero_8
     93#endif /* ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517)) */
     94GLOBAL_FUNCTION mpc55xx_zero_4
     95        /* Create zero */
     96        xor r0, r0, r0
     97
     98        /* Loop counter for the first bytes up to 16 bytes */
     99        rlwinm. r9, r4, 29, 30, 31
     100        beq zero_more4
     101        mtctr r9
     102        xor   r5,r5,r5
     103
     104zero_data4:
     105        stwx r0, r5, r3
     106        addi r5, r5, 4
     107        bdnz zero_data4
     108
     109zero_more4:
     110        /* More than 16 bytes? */
     111        srwi. r9, r4, 4
     112        beqlr
     113        mtctr r9
     114
     115zero_big_data4:
     116        stw r0,  0(r3)
     117        stw r0,  4(r3)
     118        stw r0,  8(r3)
     119        stw r0, 12(r3)
     120        addi r3, r3, 16
     121        bdnz zero_big_data4
     122        /* Return */
     123        blr
     124#if      !((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))
    52125/**
    53126 * @fn int mpc55xx_zero_8( void *dest, size_t n)
     
    96169        addi r8, r8, 32
    97170        bdnz zero_big_data
    98 
    99171        /* Return */
    100172        blr
     
    149221        /* Return */
    150222        blr
     223#endif  /*  !((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517)) */
  • c/src/lib/libcpu/powerpc/mpc55xx/misc/fmpll.S

    r08013e8 r29313369  
    5454        LA r4, FMPLL_ESYNCR2
    5555
    56         DO_SETTING 0(r3)
     56        lwz r5, 0(r3)
     57        stw r5, 0(r4)
     58        msync
    5759
    5860        lwz r5, 8(r3)
    5961        stw r5, (FMPLL_ESYNCR1-FMPLL_ESYNCR2)(r4)       
    6062        msync
     63        bl mpc55xx_fmpll_wait_for_lock
    6164
    6265        DO_SETTING 4(r3)
    6366
     67        /*
     68         * switch to PLL clock in SIU
     69         */
     70        LA r4, SIU_SYSCLK
     71        lwz r5, 0(r4)
     72        LWI r6, ~SIU_SYSCLK_SYSCLKSEL_MASK
     73        and r5, r5, r6
     74        LWI r6, SIU_SYSCLK_SYSCLKSEL_PLL
     75        or  r5, r5, r6
     76        stw r5, 0(r4)
    6477#else
    6578        /*
     
    7386        DO_SETTING 0(r3)
    7487        DO_SETTING 4(r3)
    75 #endif
     88
    7689        /* Enable loss-of-clock and loss-of-lock IRQs */
    7790        lwz r5, 0(r4)
     
    8396        and r5, r5, r6
    8497        stw r5, 0(r4)
     98#endif
    8599
    86100        /* Restore link register and return */
     
    125139
    126140        /* MFD */
    127         rlwinm r6, r3,32, 24, 31
     141        rlwinm r6, r3,0, 24, 31
    128142
    129143        LA r4, FMPLL_ESYNCR2
    130144        lwz r3, 0(r4)
    131145        /* ERFD */
    132         rlwinm r7, r3,32, 26, 31
     146        rlwinm r7, r3,0, 26, 31
    133147
    134148        LWI r8, MPC55XX_FMPLL_REF_CLOCK
     
    136150        addi r6, r6,16
    137151        addi r7, r7, 1
    138         mullw r6, r6, r8
    139         divw r3, r6, r5
    140         divw r3, r3, r7
     152        divw r3, r8, r5  /* REF_CLOCK/PREDIV */
     153        mullw r3, r6, r3 /* REF_CLOCK/PREDIV*MFD */
     154        divw r3, r3, r7  /* REF_CLOCK/PREDIV*MFD/RFD */
    141155       
    142156#else
  • c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c

    r08013e8 r29313369  
    3939 * default isOn function
    4040 */
    41 static int not_connected() {return 0;}
     41static int not_connected(void) {return 0;}
    4242
    4343/*
    4444 * default possible isOn function
    4545 */
    46 static int connected() {return 1;}
     46static int connected(void) {return 1;}
    4747
    4848static rtems_irq_connect_data           rtemsIrq[CPU_IRQ_COUNT];
     
    7777};
    7878
    79 void CPU_USIU_irq_init()
     79void CPU_USIU_irq_init(void)
    8080{
    8181  /*
  • c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c

    r08013e8 r29313369  
    9797}
    9898
    99 void initialize_exceptions()
     99void initialize_exceptions(void)
    100100{
    101101  int i;
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c

    r08013e8 r29313369  
    6767
    6868  if (ppc_cpu_has_ivpr_and_ivor()) {
     69    /*
     70     * XXX: this directly matches the vector offsets in a e200z1,
     71     * which has hardwired IVORs (IVOR0=0,IVOR1=0x10,IVOR2=0x20...)
     72     */
    6973    vector_offset >>= 4;
    7074  }
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c

    r08013e8 r29313369  
    276276    case PPC_8540:
    277277      return &e500_category_table;
     278    case PPC_e200z0:
     279    case PPC_e200z1:
    278280    case PPC_e200z6:
    279281      return &e200_category_table;
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c

    r08013e8 r29313369  
    6767  MTIVPR(ppc_exc_vector_base);
    6868
    69   /* Interupt vector offset register */
    70   MTIVOR(0,  0); /* Critical input */
    71   MTIVOR(1,  ppc_exc_vector_address( ASM_MACH_VECTOR));
    72   MTIVOR(2,  ppc_exc_vector_address( ASM_PROT_VECTOR));
    73   MTIVOR(3,  ppc_exc_vector_address( ASM_ISI_VECTOR));
    74   MTIVOR(4,  ppc_exc_vector_address( ASM_EXT_VECTOR));
    75   MTIVOR(5,  ppc_exc_vector_address( ASM_ALIGN_VECTOR));
    76   MTIVOR(6,  ppc_exc_vector_address( ASM_PROG_VECTOR));
    77   MTIVOR(7,  ppc_exc_vector_address( ASM_FLOAT_VECTOR));
    78   MTIVOR(8,  ppc_exc_vector_address( ASM_SYS_VECTOR));
    79   MTIVOR(9,  0); /* APU unavailable */
    80   MTIVOR(10, ppc_exc_vector_address( ASM_BOOKE_DEC_VECTOR));
    81   MTIVOR(11, ppc_exc_vector_address( ASM_BOOKE_FIT_VECTOR));
    82   MTIVOR(12, ppc_exc_vector_address( ASM_BOOKE_WDOG_VECTOR));
    83   MTIVOR(13, ppc_exc_vector_address( ASM_BOOKE_ITLBMISS_VECTOR));
    84   MTIVOR(14, ppc_exc_vector_address( ASM_BOOKE_DTLBMISS_VECTOR));
    85   MTIVOR(15, ppc_exc_vector_address( ASM_TRACE_VECTOR));
    86   MTIVOR(32, ppc_exc_vector_address( ASM_E200_SPE_UNAVAILABLE_VECTOR));
    87   MTIVOR(33, ppc_exc_vector_address( ASM_E200_SPE_DATA_VECTOR));
    88   MTIVOR(34, ppc_exc_vector_address( ASM_E200_SPE_ROUND_VECTOR));
     69  if (ppc_cpu_has_ivor()) {
     70    /* Interupt vector offset register */
     71    MTIVOR(0,  0); /* Critical input */
     72    MTIVOR(1,  ppc_exc_vector_address( ASM_MACH_VECTOR));
     73    MTIVOR(2,  ppc_exc_vector_address( ASM_PROT_VECTOR));
     74    MTIVOR(3,  ppc_exc_vector_address( ASM_ISI_VECTOR));
     75    MTIVOR(4,  ppc_exc_vector_address( ASM_EXT_VECTOR));
     76    MTIVOR(5,  ppc_exc_vector_address( ASM_ALIGN_VECTOR));
     77    MTIVOR(6,  ppc_exc_vector_address( ASM_PROG_VECTOR));
     78    MTIVOR(7,  ppc_exc_vector_address( ASM_FLOAT_VECTOR));
     79    MTIVOR(8,  ppc_exc_vector_address( ASM_SYS_VECTOR));
     80    MTIVOR(9,  0); /* APU unavailable */
     81    MTIVOR(10, ppc_exc_vector_address( ASM_BOOKE_DEC_VECTOR));
     82    MTIVOR(11, ppc_exc_vector_address( ASM_BOOKE_FIT_VECTOR));
     83    MTIVOR(12, ppc_exc_vector_address( ASM_BOOKE_WDOG_VECTOR));
     84    MTIVOR(13, ppc_exc_vector_address( ASM_BOOKE_ITLBMISS_VECTOR));
     85    MTIVOR(14, ppc_exc_vector_address( ASM_BOOKE_DTLBMISS_VECTOR));
     86    MTIVOR(15, ppc_exc_vector_address( ASM_TRACE_VECTOR));
     87    MTIVOR(32, ppc_exc_vector_address( ASM_E200_SPE_UNAVAILABLE_VECTOR));
     88    MTIVOR(33, ppc_exc_vector_address( ASM_E200_SPE_DATA_VECTOR));
     89    MTIVOR(34, ppc_exc_vector_address( ASM_E200_SPE_ROUND_VECTOR));
     90  }
    8991}
    9092
     
    141143#endif
    142144 
    143   if (ppc_cpu_is(PPC_e200z6)) {
     145  if (ppc_cpu_is(PPC_e200z1) ||
     146      ppc_cpu_is(PPC_e200z6)) {
    144147    ppc_exc_initialize_e200();
    145148  } else if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c

    r08013e8 r29313369  
    3636  .has_epic = 0,
    3737  .has_shadowed_gprs = 0,
    38   .has_ivpr_and_ivor = 0
     38  .has_ivpr = 0,
     39  .has_ivor = 0
    3940};
    4041
     
    6364    case PPC_8540:              return "MPC8540";
    6465    case PPC_PSIM:              return "PSIM";
     66    case PPC_e200z0:            return "e200z0";
     67    case PPC_e200z1:            return "e200z1";
    6568    case PPC_e200z6:            return "e200z6";
    6669    default:
     
    103106    case PPC_PSIM:
    104107    case PPC_8540:
     108    case PPC_e200z0:
     109    case PPC_e200z1:
    105110    case PPC_e200z6:
    106111    case PPC_e300c1:
     
    159164        break;
    160165        case PPC_8540:
     166        case PPC_e200z0:
     167        case PPC_e200z1:
    161168        case PPC_e200z6:
    162169                current_ppc_features.is_bookE                   = PPC_BOOKE_E500;
     
    186193
    187194        switch (current_ppc_cpu) {
     195                case PPC_e200z0:
     196                case PPC_e200z1:
     197                        current_ppc_features.has_ivpr = 1;
     198                        current_ppc_features.has_hwivor = 1;
     199                        break;
    188200                case PPC_e200z6:
    189                         current_ppc_features.has_ivpr_and_ivor = 1;
     201                        current_ppc_features.has_ivpr = 1;
     202                        current_ppc_features.has_ivor = 1;
    190203                        break;
    191204                default:
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    r08013e8 r29313369  
    5656  PPC_e300c2  = 0x8084, /* e300c2  core */
    5757  PPC_e300c3  = 0x8085, /* e300c3  core */
    58   PPC_e200z6 = 0x8115,
    59   PPC_PSIM = 0xfffe,  /* GDB PowerPC simulator -- fake version */
     58  PPC_e200z0  = 0x8171,
     59  PPC_e200z1  = 0x8144,
     60  PPC_e200z6  = 0x8115,
     61  PPC_PSIM    = 0xfffe,  /* GDB PowerPC simulator -- fake version */
    6062  PPC_UNKNOWN = 0xffff
    6163} ppc_cpu_id_t;
     
    8082        unsigned has_epic           : 1;
    8183        unsigned has_shadowed_gprs  : 1;
    82         unsigned has_ivpr_and_ivor  : 1;
     84        unsigned has_ivpr           : 1;
     85        unsigned has_ivor           : 1;
     86        unsigned has_hwivor         : 1;
    8387} ppc_feature_t;
    8488
     
    109113_PPC_FEAT_DECL(has_epic)
    110114_PPC_FEAT_DECL(has_shadowed_gprs)
    111 _PPC_FEAT_DECL(has_ivpr_and_ivor)
     115_PPC_FEAT_DECL(has_ivpr)
     116_PPC_FEAT_DECL(has_ivor)
     117_PPC_FEAT_DECL(has_hwivor)
    112118
    113119#undef _PPC_FEAT_DECL
     120
     121static inline unsigned ppc_cpu_has_ivpr_and_ivor() { \
     122  return ppc_cpu_has_ivpr()
     123    && (ppc_cpu_has_ivor() || ppc_cpu_has_hwivor());
     124}
    114125
    115126static inline ppc_cpu_id_t ppc_cpu_current(void)
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