[eeb3a99] | 1 | /** |
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| 2 | * @file rtems/score/sh.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[7908ba5b] | 6 | * This include file contains information pertaining to the Hitachi SH |
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| 7 | * processor. |
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| 8 | * |
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| 9 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 10 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 11 | * |
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| 12 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 13 | * |
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| 14 | * This program is distributed in the hope that it will be useful, |
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| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE |
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| 17 | * |
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| 18 | * |
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[7d953c2] | 19 | * COPYRIGHT (c) 1998-2001. |
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[7908ba5b] | 20 | * On-Line Applications Research Corporation (OAR). |
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| 21 | * |
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| 22 | * The license and distribution terms for this file may be |
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| 23 | * found in the file LICENSE in this distribution or at |
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[7f28803d] | 24 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 25 | * |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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[7f70d1b7] | 29 | #ifndef _RTEMS_SCORE_SH_H |
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| 30 | #define _RTEMS_SCORE_SH_H |
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[7908ba5b] | 31 | |
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| 32 | #ifdef __cplusplus |
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| 33 | extern "C" { |
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| 34 | #endif |
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| 35 | |
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| 36 | /* |
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| 37 | * This file contains the information required to build |
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| 38 | * RTEMS for a particular member of the "SH" family. |
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| 39 | * |
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| 40 | * It does this by setting variables to indicate which implementation |
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| 41 | * dependent features are present in a particular member of the family. |
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| 42 | */ |
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[ac815430] | 43 | |
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[df49c60] | 44 | /* |
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| 45 | * Figure out all CPU Model Feature Flags based upon compiler |
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| 46 | * predefines. |
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| 47 | */ |
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| 48 | |
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[bc5fc7a6] | 49 | #if defined(__SH3E__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) |
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| 50 | |
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| 51 | /* |
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| 52 | * Define this if you want to use XD-registers. |
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| 53 | * Then this registers will be saved/restored on context switch. |
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| 54 | * ! They will not be saved/restored on interrupts! |
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| 55 | */ |
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| 56 | #define SH4_USE_X_REGISTERS 0 |
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[df49c60] | 57 | |
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[bc5fc7a6] | 58 | #if defined(__LITTLE_ENDIAN__) |
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| 59 | #define SH_HAS_FPU 1 |
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[ac815430] | 60 | #else |
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[bc5fc7a6] | 61 | /* FIXME: Context_Control_fp does not support big endian */ |
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| 62 | #warning FPU not supported |
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| 63 | #define SH_HAS_FPU 0 |
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| 64 | #endif |
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[7908ba5b] | 65 | |
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[bc5fc7a6] | 66 | #elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) |
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| 67 | #define SH_HAS_FPU 0 |
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[97c465c] | 68 | #else |
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[bc5fc7a6] | 69 | #warning Cannot detect FPU support, assuming no FPU |
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| 70 | #define SH_HAS_FPU 0 |
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[97c465c] | 71 | #endif |
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| 72 | |
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[ac815430] | 73 | /* this should not be here */ |
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[bc5fc7a6] | 74 | #ifndef CPU_MODEL_NAME |
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[ac815430] | 75 | #define CPU_MODEL_NAME "SH-Multilib" |
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[bc5fc7a6] | 76 | #endif |
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[ac815430] | 77 | |
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[7908ba5b] | 78 | /* |
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| 79 | * If the following macro is set to 0 there will be no software irq stack |
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| 80 | */ |
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| 81 | |
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[97c465c] | 82 | #ifndef SH_HAS_SEPARATE_STACKS |
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| 83 | #define SH_HAS_SEPARATE_STACKS 1 |
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[7908ba5b] | 84 | #endif |
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| 85 | |
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| 86 | /* |
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| 87 | * Define the name of the CPU family. |
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| 88 | */ |
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| 89 | |
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| 90 | #define CPU_NAME "Hitachi SH" |
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| 91 | |
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| 92 | #ifndef ASM |
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| 93 | |
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[bc5fc7a6] | 94 | #if defined(__sh1__) || defined(__sh2__) |
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| 95 | |
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[7908ba5b] | 96 | /* |
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| 97 | * Mask for disabling interrupts |
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| 98 | */ |
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| 99 | #define SH_IRQDIS_VALUE 0xf0 |
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| 100 | |
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| 101 | #define sh_disable_interrupts( _level ) \ |
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| 102 | asm volatile ( \ |
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| 103 | "stc sr,%0\n\t" \ |
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| 104 | "ldc %1,sr\n\t"\ |
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[75f2b0b] | 105 | : "=&r" (_level ) \ |
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[7908ba5b] | 106 | : "r" (SH_IRQDIS_VALUE) ); |
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| 107 | |
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| 108 | #define sh_enable_interrupts( _level ) \ |
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| 109 | asm volatile( "ldc %0,sr\n\t" \ |
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| 110 | "nop\n\t" \ |
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| 111 | :: "r" (_level) ); |
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| 112 | |
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| 113 | /* |
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| 114 | * This temporarily restores the interrupt to _level before immediately |
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| 115 | * disabling them again. This is used to divide long RTEMS critical |
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| 116 | * sections into two or more parts. The parameter _level is not |
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| 117 | * modified. |
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| 118 | */ |
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| 119 | |
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| 120 | #define sh_flash_interrupts( _level ) \ |
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| 121 | asm volatile( \ |
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| 122 | "ldc %1,sr\n\t" \ |
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| 123 | "nop\n\t" \ |
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| 124 | "ldc %0,sr\n\t" \ |
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| 125 | "nop\n\t" \ |
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| 126 | : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); |
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| 127 | |
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[bc5fc7a6] | 128 | #else |
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| 129 | |
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| 130 | #define SH_IRQDIS_MASK 0xf0 |
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| 131 | |
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| 132 | #define sh_disable_interrupts( _level ) \ |
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| 133 | asm volatile ( \ |
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| 134 | "stc sr,%0\n\t" \ |
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| 135 | "mov %0,r5\n\t" \ |
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| 136 | "or %1,r5\n\t" \ |
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| 137 | "ldc r5,sr\n\t"\ |
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| 138 | : "=&r" (_level ) \ |
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| 139 | : "r" (SH_IRQDIS_MASK) \ |
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| 140 | : "r5" ); |
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| 141 | |
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| 142 | #define sh_enable_interrupts( _level ) \ |
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| 143 | asm volatile( "ldc %0,sr\n\t" \ |
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| 144 | "nop\n\t" \ |
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| 145 | :: "r" (_level) ); |
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| 146 | |
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| 147 | /* |
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| 148 | * This temporarily restores the interrupt to _level before immediately |
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| 149 | * disabling them again. This is used to divide long RTEMS critical |
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| 150 | * sections into two or more parts. The parameter _level is not |
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| 151 | * modified. |
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| 152 | */ |
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| 153 | |
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| 154 | #define sh_flash_interrupts( _level ) \ |
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| 155 | asm volatile( \ |
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| 156 | "stc sr,r5\n\t" \ |
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| 157 | "ldc %1,sr\n\t" \ |
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| 158 | "nop\n\t" \ |
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| 159 | "or %0,r5\n\t" \ |
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| 160 | "ldc r5,sr\n\t" \ |
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| 161 | "nop\n\t" \ |
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| 162 | : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); |
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| 163 | |
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| 164 | #endif |
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| 165 | |
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[7908ba5b] | 166 | #define sh_get_interrupt_level( _level ) \ |
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| 167 | { \ |
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[9a26317] | 168 | register uint32_t _tmpsr ; \ |
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[7908ba5b] | 169 | \ |
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| 170 | asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ |
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| 171 | _level = (_tmpsr & 0xf0) >> 4 ; \ |
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| 172 | } |
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| 173 | |
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| 174 | #define sh_set_interrupt_level( _newlevel ) \ |
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| 175 | { \ |
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[9a26317] | 176 | register uint32_t _tmpsr; \ |
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[7908ba5b] | 177 | \ |
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| 178 | asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ |
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| 179 | _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ |
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| 180 | asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ |
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| 181 | } |
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| 182 | |
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| 183 | /* |
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| 184 | * The following routine swaps the endian format of an unsigned int. |
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| 185 | * It must be static because it is referenced indirectly. |
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| 186 | */ |
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| 187 | |
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[18ebea1] | 188 | static inline uint32_t sh_swap_u32( |
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| 189 | uint32_t value |
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[7908ba5b] | 190 | ) |
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| 191 | { |
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[18ebea1] | 192 | register uint32_t swapped; |
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[7908ba5b] | 193 | |
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| 194 | asm volatile ( |
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| 195 | "swap.b %1,%0; " |
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| 196 | "swap.w %0,%0; " |
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| 197 | "swap.b %0,%0" |
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| 198 | : "=r" (swapped) |
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| 199 | : "r" (value) ); |
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| 200 | |
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| 201 | return( swapped ); |
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| 202 | } |
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| 203 | |
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[a992b8e] | 204 | static inline uint16_t sh_swap_u16( |
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| 205 | uint16_t value |
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[7908ba5b] | 206 | ) |
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| 207 | { |
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[a992b8e] | 208 | register uint16_t swapped ; |
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[7908ba5b] | 209 | |
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| 210 | asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); |
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| 211 | |
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| 212 | return( swapped ); |
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| 213 | } |
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| 214 | |
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| 215 | #define CPU_swap_u32( value ) sh_swap_u32( value ) |
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| 216 | #define CPU_swap_u16( value ) sh_swap_u16( value ) |
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| 217 | |
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| 218 | extern unsigned int sh_set_irq_priority( |
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| 219 | unsigned int irq, |
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| 220 | unsigned int prio ); |
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| 221 | |
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| 222 | #endif /* !ASM */ |
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| 223 | |
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[7d953c2] | 224 | /* |
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| 225 | * Bits on SH-4 registers. |
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| 226 | * See SH-4 Programming manual for more details. |
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| 227 | * |
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| 228 | * Added by Alexandra Kossovsky <sasha@oktet.ru> |
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| 229 | */ |
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| 230 | |
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| 231 | #if defined(__SH4__) |
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| 232 | #define SH4_SR_MD 0x40000000 /* Priveleged mode */ |
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| 233 | #define SH4_SR_RB 0x20000000 /* General register bank specifier */ |
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| 234 | #define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ |
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| 235 | #define SH4_SR_FD 0x00008000 /* FPU disable bit */ |
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| 236 | #define SH4_SR_M 0x00000200 /* For signed division: |
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| 237 | divisor (module) is negative */ |
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| 238 | #define SH4_SR_Q 0x00000100 /* For signed division: |
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| 239 | dividend (and quotient) is negative */ |
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| 240 | #define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ |
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| 241 | #define SH4_SR_IMASK_S 4 |
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| 242 | #define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: |
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| 243 | if set, data in MACH/L register |
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| 244 | is restricted to 48/32 bits |
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| 245 | for MAC.W/L instructions */ |
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| 246 | #define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ |
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| 247 | #define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ |
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| 248 | |
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[2bc49cf7] | 249 | /* FPSCR -- FPU Status/Control Register */ |
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[7d953c2] | 250 | #define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ |
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| 251 | #define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ |
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| 252 | #define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point |
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| 253 | operations flag */ |
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| 254 | /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ |
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| 255 | #define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ |
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| 256 | #define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ |
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| 257 | #define SH4_FPSCR_CAUSE_S 12 |
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| 258 | #define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ |
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| 259 | #define SH4_FPSCR_ENABLE_s 7 |
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| 260 | #define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ |
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| 261 | #define SH4_FPSCR_FLAG_S 2 |
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| 262 | #define SH4_FPSCR_RM 0x00000001 /* Rounding mode: |
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| 263 | 1/0 -- round to zero/nearest */ |
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| 264 | #define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ |
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| 265 | |
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| 266 | #endif |
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| 267 | |
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[7908ba5b] | 268 | #ifdef __cplusplus |
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| 269 | } |
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| 270 | #endif |
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| 271 | |
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| 272 | #endif |
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