source: rtems/cpukit/score/cpu/sh/rtems/score/sh.h @ 7f70d1b7

4.104.114.84.95
Last change on this file since 7f70d1b7 was 7f70d1b7, checked in by Ralf Corsepius <ralf.corsepius@…>, on 01/28/05 at 15:56:09

New header guard.

  • Property mode set to 100644
File size: 7.1 KB
Line 
1/**
2 * @file rtems/score/sh.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Hitachi SH
7 *  processor.
8 *
9 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 *           Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 *  This program is distributed in the hope that it will be useful,
15 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
17 *
18 *
19 *  COPYRIGHT (c) 1998-2001.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.com/license/LICENSE.
25 *
26 *  $Id$
27 */
28
29#ifndef _RTEMS_SCORE_SH_H
30#define _RTEMS_SCORE_SH_H
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36/*
37 *  This file contains the information required to build
38 *  RTEMS for a particular member of the "SH" family.
39 * 
40 *  It does  this by setting variables to indicate which implementation
41 *  dependent features are present in a particular member of the family.
42 */
43
44/*
45 *  Figure out all CPU Model Feature Flags based upon compiler
46 *  predefines.
47 */
48
49#if defined(__SH3E__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
50
51/*
52 * Define this if you want to use XD-registers.
53 * Then this registers will be saved/restored on context switch.
54 * ! They will not be saved/restored on interrupts!
55 */
56#define SH4_USE_X_REGISTERS     0
57
58#if defined(__LITTLE_ENDIAN__)
59#define SH_HAS_FPU 1
60#else
61/* FIXME: Context_Control_fp does not support big endian */
62#warning FPU not supported
63#define SH_HAS_FPU 0
64#endif
65
66#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
67#define SH_HAS_FPU 0
68#else
69#warning Cannot detect FPU support, assuming no FPU
70#define SH_HAS_FPU 0
71#endif
72
73/* this should not be here */
74#ifndef CPU_MODEL_NAME
75#define CPU_MODEL_NAME  "SH-Multilib"
76#endif
77
78/*
79 * If the following macro is set to 0 there will be no software irq stack
80 */
81
82#ifndef SH_HAS_SEPARATE_STACKS
83#define SH_HAS_SEPARATE_STACKS 1
84#endif
85
86/*
87 *  Define the name of the CPU family.
88 */
89
90#define CPU_NAME "Hitachi SH"
91
92#ifndef ASM
93
94#if defined(__sh1__) || defined(__sh2__)
95
96/*
97 * Mask for disabling interrupts
98 */
99#define SH_IRQDIS_VALUE 0xf0
100
101#define sh_disable_interrupts( _level ) \
102  asm volatile ( \
103    "stc sr,%0\n\t" \
104    "ldc %1,sr\n\t"\
105  : "=&r" (_level ) \
106  : "r" (SH_IRQDIS_VALUE) );
107
108#define sh_enable_interrupts( _level ) \
109  asm volatile( "ldc %0,sr\n\t" \
110    "nop\n\t" \
111    :: "r" (_level) );
112
113/*
114 *  This temporarily restores the interrupt to _level before immediately
115 *  disabling them again.  This is used to divide long RTEMS critical
116 *  sections into two or more parts.  The parameter _level is not
117 *  modified.
118 */
119     
120#define sh_flash_interrupts( _level ) \
121  asm volatile( \
122    "ldc %1,sr\n\t" \
123    "nop\n\t" \
124    "ldc %0,sr\n\t" \
125    "nop\n\t" \
126    : : "r" (SH_IRQDIS_VALUE), "r" (_level) );
127
128#else
129
130#define SH_IRQDIS_MASK 0xf0
131
132#define sh_disable_interrupts( _level ) \
133  asm volatile ( \
134    "stc sr,%0\n\t" \
135    "mov %0,r5\n\t" \
136    "or %1,r5\n\t" \
137    "ldc r5,sr\n\t"\
138  : "=&r" (_level ) \
139  : "r" (SH_IRQDIS_MASK) \
140  : "r5" );
141
142#define sh_enable_interrupts( _level ) \
143  asm volatile( "ldc %0,sr\n\t" \
144    "nop\n\t" \
145    :: "r" (_level) );
146
147/*
148 *  This temporarily restores the interrupt to _level before immediately
149 *  disabling them again.  This is used to divide long RTEMS critical
150 *  sections into two or more parts.  The parameter _level is not
151 *  modified.
152 */
153     
154#define sh_flash_interrupts( _level ) \
155  asm volatile( \
156    "stc sr,r5\n\t" \
157    "ldc %1,sr\n\t" \
158    "nop\n\t" \
159    "or %0,r5\n\t" \
160    "ldc r5,sr\n\t" \
161    "nop\n\t" \
162    : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5");
163
164#endif
165
166#define sh_get_interrupt_level( _level ) \
167{ \
168  register uint32_t   _tmpsr ; \
169  \
170  asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
171  _level = (_tmpsr & 0xf0) >> 4 ; \
172}
173
174#define sh_set_interrupt_level( _newlevel ) \
175{ \
176  register uint32_t   _tmpsr; \
177  \
178  asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
179  _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
180  asm  volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
181}
182
183/*
184 *  The following routine swaps the endian format of an unsigned int.
185 *  It must be static because it is referenced indirectly.
186 */
187 
188static inline uint32_t sh_swap_u32(
189  uint32_t value
190)
191{
192  register uint32_t swapped;
193 
194  asm volatile (
195    "swap.b %1,%0; "
196    "swap.w %0,%0; "
197    "swap.b %0,%0"
198    : "=r" (swapped)
199    : "r"  (value) );
200
201  return( swapped );
202}
203
204static inline uint16_t sh_swap_u16(
205  uint16_t value
206)
207{
208  register uint16_t swapped ;
209
210  asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r"  (value) );
211
212  return( swapped );
213}
214
215#define CPU_swap_u32( value ) sh_swap_u32( value )
216#define CPU_swap_u16( value ) sh_swap_u16( value )
217
218extern unsigned int sh_set_irq_priority(
219  unsigned int irq,
220  unsigned int prio );
221
222#endif /* !ASM */
223
224/*
225 * Bits on SH-4 registers.
226 * See SH-4 Programming manual for more details.
227 *
228 * Added by Alexandra Kossovsky <sasha@oktet.ru>
229 */
230
231#if defined(__SH4__)
232#define SH4_SR_MD          0x40000000 /* Priveleged mode */
233#define SH4_SR_RB          0x20000000 /* General register bank specifier */
234#define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
235#define SH4_SR_FD          0x00008000 /* FPU disable bit */
236#define SH4_SR_M           0x00000200 /* For signed division:
237                                         divisor (module) is negative */
238#define SH4_SR_Q           0x00000100 /* For signed division:
239                                         dividend (and quotient) is negative */
240#define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
241#define SH4_SR_IMASK_S     4
242#define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
243                                         if set, data in MACH/L register
244                                         is restricted to 48/32 bits
245                                         for MAC.W/L instructions */
246#define SH4_SR_T           0x00000001 /* 1 if last condiyion was true */
247#define SH4_SR_RESERV      0x8fff7d0d /* Reserved bits, read/write as 0 */
248
249/* FPSCR -- FPU Status/Control Register */
250#define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
251#define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
252#define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
253                                         operations flag */
254                                      /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
255#define SH4_FPSCR_DN       0x00040000 /* Treat denormalized number as zero */
256#define SH4_FPSCR_CAUSE    0x0003f000 /* FPU exeption cause field */
257#define SH4_FPSCR_CAUSE_S  12
258#define SH4_FPSCR_ENABLE   0x00000f80 /* FPU exeption enable field */
259#define SH4_FPSCR_ENABLE_s 7
260#define SH4_FPSCR_FLAG     0x0000007d /* FPU exeption flag field */
261#define SH4_FPSCR_FLAG_S   2
262#define SH4_FPSCR_RM       0x00000001 /* Rounding mode:
263                                         1/0 -- round to zero/nearest */
264#define SH4_FPSCR_RESERV   0xffd00000 /* Reserved bits, read/write as 0 */
265
266#endif
267
268#ifdef __cplusplus
269}
270#endif
271
272#endif
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