[7be6ad9] | 1 | /* irq.c |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[f8e0327] | 9 | * http://www.rtems.com/license/LICENSE. |
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[7be6ad9] | 10 | * |
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| 11 | * Special acknowledgement to Till Straumann <strauman@slac.stanford.edu> |
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| 12 | * for providing inputs to the IRQ handling and optimization. |
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| 13 | * |
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| 14 | * Modified and added support for the MVME5500 board |
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| 15 | * Copyright 2003, 2004, Shuchen Kate Feng <feng1@bnl.gov>, |
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| 16 | * NSLS,Brookhaven National Laboratory |
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| 17 | * |
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| 18 | */ |
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| 19 | |
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| 20 | #include <rtems/system.h> |
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| 21 | #include <bsp.h> |
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| 22 | #include <bsp/irq.h> |
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| 23 | #include <rtems/score/thread.h> |
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| 24 | #include <rtems/score/apiext.h> |
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| 25 | #include <libcpu/raw_exception.h> |
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| 26 | #include <libcpu/io.h> |
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| 27 | #include <bsp/vectors.h> |
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| 28 | |
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| 29 | #include <rtems/bspIo.h> /* for printk */ |
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| 30 | #include "bsp/gtreg.h" |
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| 31 | |
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| 32 | #define HI_INT_CAUSE 0x40000000 |
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| 33 | |
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| 34 | /*#define DEBUG*/ |
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| 35 | |
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| 36 | int gpp_int_error =0; |
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| 37 | |
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| 38 | /* |
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| 39 | * pointer to the mask representing the additionnal irq vectors |
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| 40 | * that must be disabled when a particular entry is activated. |
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| 41 | * They will be dynamically computed from teh prioruty table given |
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| 42 | * in BSP_rtems_irq_mngt_set(); |
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| 43 | * CAUTION : this table is accessed directly by interrupt routine |
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| 44 | * prologue. |
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| 45 | */ |
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| 46 | static unsigned int irq_prio_maskLO_tbl[BSP_MAIN_IRQ_NUMBER]; |
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| 47 | static unsigned int irq_prio_maskHI_tbl[BSP_MAIN_IRQ_NUMBER]; |
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| 48 | |
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| 49 | /* |
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| 50 | * default handler connected on each irq after bsp initialization |
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| 51 | */ |
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| 52 | static rtems_irq_connect_data default_rtems_entry; |
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| 53 | |
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| 54 | /* |
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| 55 | * location used to store initial tables used for interrupt |
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| 56 | * management. |
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| 57 | */ |
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| 58 | static rtems_irq_global_settings* internal_config; |
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| 59 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 60 | |
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| 61 | static unsigned int irqCAUSE[20], irqLOW[20], irqHIGH[20]; |
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| 62 | static int irqIndex=0; |
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| 63 | |
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| 64 | /* |
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| 65 | * Check if IRQ is a MAIN CPU internal IRQ |
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| 66 | */ |
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[490fd4a] | 67 | static inline int is_main_irq(const rtems_irq_number irqLine) |
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[7be6ad9] | 68 | { |
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| 69 | return (((int) irqLine <= BSP_MICH_IRQ_MAX_OFFSET) & |
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| 70 | ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET) |
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| 71 | ); |
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| 72 | } |
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| 73 | |
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| 74 | /* |
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| 75 | * Check if IRQ is a GPP IRQ |
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| 76 | */ |
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[490fd4a] | 77 | static inline int is_gpp_irq(const rtems_irq_number irqLine) |
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[7be6ad9] | 78 | { |
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| 79 | return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) & |
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| 80 | ((int) irqLine >= BSP_GPP_IRQ_LOWEST_OFFSET) |
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| 81 | ); |
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| 82 | } |
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| 83 | |
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| 84 | /* |
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| 85 | * Check if IRQ is a Porcessor IRQ |
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| 86 | */ |
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[490fd4a] | 87 | static inline int is_processor_irq(const rtems_irq_number irqLine) |
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[7be6ad9] | 88 | { |
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| 89 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 90 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 91 | ); |
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| 92 | } |
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| 93 | |
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| 94 | #define GT_GPP_Int1_Cause GT_GPP_Interrupt_Cause+1 |
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| 95 | #define GT_GPP_Int2_Cause GT_GPP_Interrupt_Cause+2 |
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| 96 | #define GT_GPP_Int3_Cause GT_GPP_Interrupt_Cause+3 |
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| 97 | |
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| 98 | void GT_GPP_IntHandler0() |
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| 99 | { |
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| 100 | |
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| 101 | unsigned gppCause, irqNum, bitNum; |
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| 102 | int i, found=0; |
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| 103 | |
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| 104 | gppCause = inb(GT_GPP_Interrupt_Cause) & GT_GPPirq_cache; |
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| 105 | |
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| 106 | for (i=0; GPP7_0IrqTbl[i]!=-1;i++){ |
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| 107 | bitNum =GPP7_0IrqTbl[i]; |
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| 108 | if (gppCause & (1<<bitNum)) { |
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| 109 | /* Clear the GPP interrupt cause bit */ |
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| 110 | outb( ~(1<<bitNum), GT_GPP_Interrupt_Cause);/* Till Straumann */ |
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| 111 | found = 1; |
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| 112 | irqNum = bitNum+BSP_GPP_IRQ_LOWEST_OFFSET; |
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| 113 | /* call the necessary interrupt handlers */ |
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| 114 | if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl) |
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[4953659b] | 115 | rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle); |
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[7be6ad9] | 116 | else |
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| 117 | gpp_int_error= bitNum; /*GPP interrupt bitNum not connected */ |
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| 118 | } |
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| 119 | } |
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| 120 | if ( !found) gpp_int_error = 33; /* spurious GPP interrupt */ |
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| 121 | } |
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| 122 | |
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| 123 | void GT_GPP_IntHandler1() |
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| 124 | { |
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| 125 | unsigned gppCause, irqNum, bitNum; |
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| 126 | int i, found=0; |
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| 127 | |
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| 128 | gppCause = inb(GT_GPP_Int1_Cause) & (GT_GPPirq_cache>>8); |
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| 129 | |
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| 130 | for (i=0; GPP15_8IrqTbl[i]!=-1;i++){ |
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| 131 | bitNum =GPP15_8IrqTbl[i]; |
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| 132 | if (gppCause & (1<<bitNum)) { |
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| 133 | /* Clear the GPP interrupt cause bit */ |
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| 134 | outb( ~(1<<bitNum), GT_GPP_Int1_Cause); /* Till Straumann */ |
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| 135 | found = 1; |
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| 136 | irqNum = bitNum+BSP_GPP8_IRQ_OFFSET; |
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| 137 | /* call the necessary interrupt handlers */ |
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| 138 | if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl) |
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[4953659b] | 139 | rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle); |
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[7be6ad9] | 140 | else |
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| 141 | gpp_int_error= bitNum+8; /*GPP interrupt bitNum not connected */ |
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| 142 | } |
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| 143 | } |
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| 144 | if ( !found) gpp_int_error = 33; /* spurious GPP interrupt */ |
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| 145 | } |
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| 146 | void GT_GPP_IntHandler2() |
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| 147 | { |
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| 148 | unsigned gppCause, irqNum, bitNum; |
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| 149 | int i, found=0; |
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| 150 | |
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| 151 | gppCause = inb(GT_GPP_Int2_Cause) & (GT_GPPirq_cache>>16); |
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| 152 | |
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| 153 | for (i=0; GPP23_16IrqTbl[i]!=-1;i++){ |
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| 154 | bitNum =GPP23_16IrqTbl[i]; |
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| 155 | if (gppCause & (1<<bitNum)) { |
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| 156 | /* Clear the GPP interrupt cause bit */ |
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| 157 | outb( ~(1<<bitNum), GT_GPP_Int2_Cause); |
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| 158 | found = 1; |
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| 159 | irqNum = bitNum+BSP_GPP16_IRQ_OFFSET; |
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| 160 | /* call the necessary interrupt handlers */ |
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| 161 | if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl) |
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[4953659b] | 162 | rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle); |
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[7be6ad9] | 163 | else |
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| 164 | gpp_int_error= bitNum+16; /*GPP interrupt bitNum not connected */ |
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| 165 | } |
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| 166 | } |
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| 167 | if ( !found) gpp_int_error = 33; /* spurious GPP interrupt */ |
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| 168 | } |
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| 169 | |
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| 170 | void GT_GPP_IntHandler3() |
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| 171 | { |
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| 172 | unsigned gppCause, irqNum, bitNum; |
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| 173 | int i, found=0; |
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| 174 | |
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| 175 | gppCause = inb(GT_GPP_Int3_Cause) & (GT_GPPirq_cache>>24); |
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| 176 | |
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| 177 | for (i=0; GPP31_24IrqTbl[i]!=-1;i++){ |
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| 178 | bitNum=GPP31_24IrqTbl[i]; |
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| 179 | if (gppCause & (1<<bitNum)) { |
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| 180 | /* Clear the GPP interrupt cause bit */ |
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| 181 | outb(~(1<<bitNum), GT_GPP_Int3_Cause); |
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| 182 | found = 1; |
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| 183 | irqNum = bitNum+BSP_GPP24_IRQ_OFFSET; |
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| 184 | /* call the necessary interrupt handlers */ |
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| 185 | if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl) |
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[4953659b] | 186 | rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle); |
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[7be6ad9] | 187 | else |
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| 188 | gpp_int_error= bitNum+24; /*GPP interrupt bitNum not connected */ |
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| 189 | } |
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| 190 | } |
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| 191 | if ( !found) gpp_int_error = 33; /* spurious GPP interrupt */ |
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| 192 | } |
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| 193 | |
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| 194 | /* |
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| 195 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 196 | */ |
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| 197 | |
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| 198 | /* |
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| 199 | * Caution : this function assumes the variable "internal_config" |
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| 200 | * is already set and that the tables it contains are still valid |
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| 201 | * and accessible. |
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| 202 | */ |
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| 203 | static void compute_GT64260int_masks_from_prio () |
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| 204 | { |
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| 205 | int i,j; |
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| 206 | unsigned long long irq_prio_mask=0; |
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| 207 | |
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| 208 | /* |
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| 209 | * Always mask at least current interrupt to prevent re-entrance |
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| 210 | */ |
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| 211 | for (i=0; i <BSP_MAIN_IRQ_NUMBER; i++) { |
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| 212 | irq_prio_mask = (unsigned long long) (1LLU << i); |
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| 213 | for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) { |
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| 214 | /* |
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| 215 | * Mask interrupts at GT64260int level that have a lower priority |
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| 216 | * or <Till Straumann> a equal priority. |
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| 217 | */ |
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| 218 | if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j]) { |
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| 219 | irq_prio_mask |= (unsigned long long)(1LLU << j); |
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| 220 | } |
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| 221 | } |
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| 222 | |
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| 223 | irq_prio_maskLO_tbl[i] = irq_prio_mask & 0xffffffff; |
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| 224 | irq_prio_maskHI_tbl[i] = (irq_prio_mask>>32) & 0xffffffff; |
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| 225 | #ifdef DEBUG |
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| 226 | printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,irq_prio_maskHI_tbl[i], |
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| 227 | irq_prio_maskLO_tbl[i]); |
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| 228 | #endif |
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| 229 | } |
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| 230 | } |
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| 231 | |
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| 232 | /* |
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| 233 | * This function check that the value given for the irq line |
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| 234 | * is valid. |
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| 235 | */ |
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| 236 | |
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| 237 | static int isValidInterrupt(int irq) |
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| 238 | { |
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| 239 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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| 240 | return 0; |
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| 241 | return 1; |
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| 242 | } |
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| 243 | |
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| 244 | /* |
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| 245 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 246 | */ |
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| 247 | |
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| 248 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 249 | { |
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| 250 | unsigned int level; |
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| 251 | |
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| 252 | if (!isValidInterrupt(irq->name)) { |
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| 253 | printk("Invalid interrupt vector %d\n",irq->name); |
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| 254 | return 0; |
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| 255 | } |
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| 256 | /* |
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| 257 | * Check if default handler is actually connected. If not issue an error. |
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| 258 | * You must first get the current handler via i386_get_current_idt_entry |
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| 259 | * and then disconnect it using i386_delete_idt_entry. |
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| 260 | * RATIONALE : to always have the same transition by forcing the user |
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| 261 | * to get the previous handler before accepting to disconnect. |
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| 262 | */ |
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| 263 | _CPU_ISR_Disable(level); |
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| 264 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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| 265 | _CPU_ISR_Enable(level); |
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| 266 | printk("IRQ vector %d already connected\n",irq->name); |
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| 267 | return 0; |
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| 268 | } |
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| 269 | |
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| 270 | /* |
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| 271 | * store the data provided by user |
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| 272 | */ |
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| 273 | rtems_hdl_tbl[irq->name] = *irq; |
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| 274 | rtems_hdl_tbl[irq->name].next_handler = (void *)-1; |
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| 275 | |
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| 276 | if (is_main_irq(irq->name)) { |
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| 277 | /* |
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| 278 | * Enable (internal ) Main Interrupt Cause Low and High |
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| 279 | */ |
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| 280 | #ifdef DEBUG_IRQ |
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| 281 | printk("main irq %d\n",irq->name); |
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| 282 | #endif |
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| 283 | BSP_enable_main_irq(irq->name); |
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| 284 | } |
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| 285 | |
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| 286 | if (is_gpp_irq(irq->name)) { |
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| 287 | /* |
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| 288 | * Enable (external) GPP[x] interrupt |
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| 289 | */ |
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| 290 | BSP_enable_gpp_irq((int) irq->name); |
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| 291 | } |
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| 292 | |
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| 293 | if (is_processor_irq(irq->name)) { |
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| 294 | /* |
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| 295 | * Enable exception at processor level |
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| 296 | */ |
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| 297 | } |
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| 298 | /* |
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| 299 | * Enable interrupt on device |
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| 300 | |
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| 301 | irq->on(irq);*/ |
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| 302 | |
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| 303 | _CPU_ISR_Enable(level); |
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| 304 | |
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| 305 | return 1; |
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| 306 | } |
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| 307 | |
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| 308 | |
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| 309 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 310 | { |
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| 311 | if (!isValidInterrupt(irq->name)) { |
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| 312 | return 0; |
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| 313 | } |
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| 314 | *irq = rtems_hdl_tbl[irq->name]; |
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| 315 | return 1; |
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| 316 | } |
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| 317 | |
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| 318 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 319 | { |
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| 320 | unsigned int level; |
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| 321 | |
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| 322 | if (!isValidInterrupt(irq->name)) { |
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| 323 | return 0; |
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| 324 | } |
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| 325 | /* |
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| 326 | * Check if default handler is actually connected. If not issue an error. |
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| 327 | * You must first get the current handler via i386_get_current_idt_entry |
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| 328 | * and then disconnect it using i386_delete_idt_entry. |
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| 329 | * RATIONALE : to always have the same transition by forcing the user |
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| 330 | * to get the previous handler before accepting to disconnect. |
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| 331 | */ |
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| 332 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 333 | return 0; |
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| 334 | } |
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| 335 | _CPU_ISR_Disable(level); |
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| 336 | |
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| 337 | if (is_main_irq(irq->name)) { |
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| 338 | /* |
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| 339 | * disable CPU main interrupt |
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| 340 | */ |
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| 341 | BSP_disable_main_irq(irq->name); |
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| 342 | } |
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| 343 | if (is_gpp_irq(irq->name)) { |
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| 344 | /* |
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| 345 | * disable external interrupt |
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| 346 | */ |
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| 347 | BSP_disable_gpp_irq(irq->name); |
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| 348 | } |
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| 349 | if (is_processor_irq(irq->name)) { |
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| 350 | /* |
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| 351 | * disable exception at processor level |
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| 352 | */ |
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| 353 | } |
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| 354 | |
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| 355 | /* |
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| 356 | * Disable interrupt on device |
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| 357 | */ |
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| 358 | irq->off(irq); |
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| 359 | |
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| 360 | /* |
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| 361 | * restore the default irq value |
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| 362 | */ |
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| 363 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 364 | |
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| 365 | _CPU_ISR_Enable(level); |
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| 366 | |
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| 367 | return 1; |
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| 368 | } |
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| 369 | |
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| 370 | /* |
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| 371 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 372 | */ |
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| 373 | |
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| 374 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 375 | { |
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| 376 | int i; |
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| 377 | unsigned int level; |
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| 378 | /* |
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| 379 | * Store various code accelerators |
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| 380 | */ |
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| 381 | internal_config = config; |
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| 382 | default_rtems_entry = config->defaultEntry; |
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| 383 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 384 | |
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| 385 | _CPU_ISR_Disable(level); |
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| 386 | compute_GT64260int_masks_from_prio(); |
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| 387 | |
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| 388 | /* |
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| 389 | * set up internal tables used by rtems interrupt prologue |
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| 390 | */ |
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| 391 | /* |
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| 392 | * start with MAIN CPU IRQ |
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| 393 | */ |
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| 394 | for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_GPP_IRQ_LOWEST_OFFSET ; i++) { |
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| 395 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 396 | BSP_enable_main_irq(i); |
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| 397 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 398 | } |
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| 399 | else { |
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| 400 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 401 | BSP_disable_main_irq(i); |
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| 402 | } |
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| 403 | } |
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| 404 | /* |
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| 405 | * continue with external IRQ |
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| 406 | */ |
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| 407 | for (i=BSP_GPP_IRQ_LOWEST_OFFSET; i<BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i++) { |
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| 408 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 409 | BSP_enable_gpp_irq(i); |
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| 410 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 411 | } |
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| 412 | else { |
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| 413 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 414 | BSP_disable_gpp_irq(i); |
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| 415 | } |
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| 416 | } |
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| 417 | |
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| 418 | /* |
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| 419 | * finish with Processor exceptions handled like IRQ |
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| 420 | */ |
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| 421 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_MAX_OFFSET+1; i++) { |
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| 422 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 423 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 424 | } |
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| 425 | else { |
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| 426 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 427 | } |
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| 428 | } |
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| 429 | _CPU_ISR_Enable(level); |
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| 430 | return 1; |
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| 431 | } |
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| 432 | |
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| 433 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 434 | { |
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| 435 | *config = internal_config; |
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| 436 | return 0; |
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| 437 | } |
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| 438 | |
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| 439 | int _BSP_vme_bridge_irq = -1; |
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| 440 | |
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| 441 | /* |
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| 442 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 443 | */ |
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| 444 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 445 | { |
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| 446 | register unsigned msr; |
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| 447 | register unsigned new_msr; |
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[234e509f] | 448 | unsigned mainCause[2]; |
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| 449 | register unsigned selectCause; |
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[7be6ad9] | 450 | register unsigned oldMask[2]={0,0}; |
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| 451 | unsigned i, regNum, irq, bitNum, startIrqNum=0; |
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| 452 | |
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| 453 | if (excNum == ASM_DEC_VECTOR) { |
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| 454 | _CPU_MSR_GET(msr); |
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| 455 | new_msr = msr | MSR_EE; |
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| 456 | _CPU_MSR_SET(new_msr); |
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| 457 | |
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[4953659b] | 458 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); |
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[7be6ad9] | 459 | |
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| 460 | _CPU_MSR_SET(msr); |
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| 461 | return; |
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| 462 | |
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| 463 | } |
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| 464 | selectCause = inl( GT_CPU_SEL_CAUSE); |
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| 465 | if (selectCause & HI_INT_CAUSE ) { |
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| 466 | mainCause[1]= selectCause & inl(GT_CPU_INT_MASK_HI); |
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| 467 | startIrqNum=32; |
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| 468 | } |
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| 469 | else { |
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| 470 | mainCause[0] =inl(GT_MAIN_INT_CAUSE_LO)&inl(GT_CPU_INT_MASK_LO); |
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| 471 | mainCause[1] =inl(GT_MAIN_INT_CAUSE_HI)&inl(GT_CPU_INT_MASK_HI); |
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| 472 | } |
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| 473 | |
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| 474 | #if 0 |
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| 475 | /* very bad practice to put printk here, use only if for debug */ |
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| 476 | printk("main 0 %x, main 1 %x \n", mainCause[0],mainCause[1]); |
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| 477 | #endif |
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| 478 | oldMask[0]= GT_MAINirqLO_cache; |
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| 479 | oldMask[1]= GT_MAINirqHI_cache; |
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| 480 | |
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| 481 | for (i=0;mainIrqTbl[i]!=-1;i++) { |
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| 482 | irq=mainIrqTbl[i]; |
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| 483 | if ( irq < startIrqNum ) continue; |
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| 484 | regNum = irq/32; |
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| 485 | bitNum = irq % 32; |
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| 486 | if ( mainCause[regNum] & (1<<bitNum)) { |
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| 487 | GT_MAINirqLO_cache=oldMask[0]&(~irq_prio_maskLO_tbl[irq]); |
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| 488 | outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO); |
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| 489 | __asm __volatile("sync"); |
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| 490 | GT_MAINirqHI_cache=oldMask[1]&(~irq_prio_maskHI_tbl[irq]); |
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| 491 | outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI); |
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| 492 | __asm __volatile("sync"); |
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| 493 | |
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| 494 | /* <skf> It seems that reading back is necessary to ensure the |
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| 495 | * interrupt mask updated. Otherwise, spurious interrupt will |
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| 496 | * happen. However, I do not want to use "while loop" to risk |
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| 497 | * the CPU stuck. I wound rather keep track of the interrupt |
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| 498 | * mask if not updated. |
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| 499 | */ |
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| 500 | if (((irqLOW[irqIndex]= inl(GT_CPU_INT_MASK_LO))!=GT_MAINirqLO_cache)|| |
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| 501 | ((irqHIGH[irqIndex]= inl(GT_CPU_INT_MASK_HI))!=GT_MAINirqHI_cache)){ |
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| 502 | irqIndex++; |
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| 503 | irqIndex %=20; |
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| 504 | irqCAUSE[irqIndex] = irq; |
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| 505 | } |
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| 506 | _CPU_MSR_GET(msr); |
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| 507 | new_msr = msr | MSR_EE; |
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| 508 | _CPU_MSR_SET(new_msr); |
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[4953659b] | 509 | rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); |
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[7be6ad9] | 510 | _CPU_MSR_SET(msr); |
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| 511 | break; |
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| 512 | } |
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| 513 | } |
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| 514 | GT_MAINirqLO_cache=oldMask[0]; |
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| 515 | outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO); |
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| 516 | GT_MAINirqHI_cache=oldMask[1]; |
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| 517 | outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI); |
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| 518 | } |
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| 519 | |
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| 520 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 521 | { |
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| 522 | /* |
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| 523 | * Process pending signals that have not already been |
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| 524 | * processed by _Thread_Displatch. This happens quite |
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| 525 | * unfrequently : the ISR must have posted an action |
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| 526 | * to the current running thread. |
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| 527 | */ |
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| 528 | if ( _Thread_Do_post_task_switch_extension || |
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| 529 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 530 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 531 | _API_extensions_Run_postswitch(); |
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| 532 | } |
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| 533 | /* |
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| 534 | * I plan to process other thread related events here. |
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| 535 | * This will include DEBUG session requested from keyboard... |
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| 536 | */ |
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| 537 | } |
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| 538 | |
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| 539 | void BSP_printIRQMask() |
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| 540 | { |
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| 541 | int i; |
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| 542 | |
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| 543 | for (i=0; i< 20; i++) |
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| 544 | printk("IRQ%d : 0x%x %x \n", irqCAUSE[i], irqHIGH[i],irqLOW[i]); |
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| 545 | } |
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