Changeset 490fd4a in rtems


Ignore:
Timestamp:
May 17, 2005, 3:03:18 PM (15 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
7068d7ac
Parents:
adc53ec9
Message:

2005-05-17 Jennifer Averett <jennifer.averett@…>

  • irq/GT64260Int.c, irq/irq.c, irq/irq.h: Modified to use rtems/irq.h.
Location:
c/src/lib/libbsp/powerpc/mvme5500
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

    radc53ec9 r490fd4a  
     12005-05-17      Jennifer Averett <jennifer.averett@oarcorp.com>
     2
     3        * irq/GT64260Int.c, irq/irq.c, irq/irq.h: Modified to use rtems/irq.h.
     4
    152005-05-12      Jennifer Averett <jennifer.averett@oarcorp.com>
    26
  • c/src/lib/libbsp/powerpc/mvme5500/irq/GT64260Int.c

    radc53ec9 r490fd4a  
    109109*
    110110*/
    111 void BSP_enable_main_irq(const rtems_irq_symbolic_name irqNum)
     111void BSP_enable_main_irq(const rtems_irq_number irqNum)
    112112{
    113113  unsigned bitNum;
     
    139139*
    140140*/
    141 void BSP_disable_main_irq(const rtems_irq_symbolic_name irqNum)
     141void BSP_disable_main_irq(const rtems_irq_number irqNum)
    142142{
    143143  unsigned bitNum;
     
    170170*
    171171*/
    172 void BSP_enable_gpp_irq(const rtems_irq_symbolic_name irqNum)
     172void BSP_enable_gpp_irq(const rtems_irq_number irqNum)
    173173{
    174174  unsigned bitNum;
     
    206206*
    207207*/
    208 void BSP_disable_gpp_irq(const rtems_irq_symbolic_name irqNum)
     208void BSP_disable_gpp_irq(const rtems_irq_number irqNum)
    209209{
    210210  unsigned bitNum;
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c

    radc53ec9 r490fd4a  
    6565 * Check if IRQ is a MAIN CPU internal IRQ
    6666 */
    67 static inline int is_main_irq(const rtems_irq_symbolic_name irqLine)
     67static inline int is_main_irq(const rtems_irq_number irqLine)
    6868{
    6969  return (((int) irqLine <= BSP_MICH_IRQ_MAX_OFFSET) &
     
    7575 * Check if IRQ is a GPP IRQ
    7676 */
    77 static inline int is_gpp_irq(const rtems_irq_symbolic_name irqLine)
     77static inline int is_gpp_irq(const rtems_irq_number irqLine)
    7878{
    7979  return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
     
    8585 * Check if IRQ is a Porcessor IRQ
    8686 */
    87 static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
     87static inline int is_processor_irq(const rtems_irq_number irqLine)
    8888{
    8989  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h

    radc53ec9 r490fd4a  
    2929#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
    3030
     31#define BSP_SHARED_HANDLER_SUPPORT      1
     32#include <rtems/irq.h>
    3133
    3234#define BSP_ASM_IRQ_VECTOR_BASE 0x0
     
    4648 */
    4749
    48 typedef enum {
    4950  /* See section 25.2 , Table 734 of GT64260 controller
    5051   * Main Interrupt Cause Low register
    5152   */
    52   BSP_MICL_IRQ_NUMBER           = 32,
    53   BSP_MICL_IRQ_LOWEST_OFFSET    =  0,
    54   BSP_MICL_IRQ_MAX_OFFSET       =  BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1,
     53#define BSP_MICL_IRQ_NUMBER           (32)
     54#define BSP_MICL_IRQ_LOWEST_OFFSET    (0)
     55#define BSP_MICL_IRQ_MAX_OFFSET       (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1)
    5556  /*
    5657   * Main Interrupt Cause High register
    5758   */
    58   BSP_MICH_IRQ_NUMBER           = 32,
    59   BSP_MICH_IRQ_LOWEST_OFFSET    = BSP_MICL_IRQ_MAX_OFFSET+1,
    60   BSP_MICH_IRQ_MAX_OFFSET       = BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1,
    61   /* External GPP Interrupt assignements
    62    */
    63   BSP_GPP_IRQ_NUMBER            =  32,
    64   BSP_GPP_IRQ_LOWEST_OFFSET     =  BSP_MICH_IRQ_MAX_OFFSET+1,
    65   BSP_GPP_IRQ_MAX_OFFSET        =  BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1,
     59#define BSP_MICH_IRQ_NUMBER           (32)
     60#define BSP_MICH_IRQ_LOWEST_OFFSET    (BSP_MICL_IRQ_MAX_OFFSET+1)
     61#define BSP_MICH_IRQ_MAX_OFFSET       (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1)
     62 /* External GPP Interrupt assignements
     63  */
     64#define BSP_GPP_IRQ_NUMBER              (32)
     65#define BSP_GPP_IRQ_LOWEST_OFFSET       (BSP_MICH_IRQ_MAX_OFFSET+1)
     66#define BSP_GPP_IRQ_MAX_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1)
    6667
    67   /*
    68    * PowerPc exceptions handled as interrupt where a rtems managed interrupt
    69    * handler might be connected
    70    */
    71   BSP_PROCESSOR_IRQ_NUMBER      =   1,
    72   BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_GPP_IRQ_MAX_OFFSET + 1,
    73   BSP_PROCESSOR_IRQ_MAX_OFFSET  =   BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
     68 /*
     69  * PowerPc exceptions handled as interrupt where a rtems managed interrupt
     70  * handler might be connected
     71  */
     72#define BSP_PROCESSOR_IRQ_NUMBER         (1)
     73#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1)
     74#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
    7475
    7576  /* allow a couple of vectors for VME and counter/timer irq sources etc.
    7677   * This is probably not needed any more.
    7778   */
    78   BSP_MISC_IRQ_NUMBER           =   30,
    79   BSP_MISC_IRQ_LOWEST_OFFSET    =   BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
    80   BSP_MISC_IRQ_MAX_OFFSET       =   BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
    81 
    82 #if 0
    83   /*
    84    * ISA IRQ handler related definitions
    85    */
    86   /* MVME5500 ISA local resources exist only if an IPMC 712/761 module
    87    * is mounted.
    88    */
    89   BSP_ISA_IRQ_NUMBER            = 0,
    90   BSP_ISA_IRQ_LOWEST_OFFSET     = BSP_MISC_IRQ_MAX_OFFSET+1,
    91   BSP_ISA_IRQ_MAX_OFFSET        = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
    92 
    93 #endif
     79#define BSP_MISC_IRQ_NUMBER             (30)
     80#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
     81#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
    9482
    9583  /*
    9684   * Summary
    9785   */
    98   BSP_IRQ_NUMBER                = BSP_MISC_IRQ_MAX_OFFSET + 1,
    99   BSP_MAIN_IRQ_NUMBER           = 64,
    100   BSP_LOWEST_OFFSET             = BSP_MICL_IRQ_LOWEST_OFFSET,
    101   BSP_MAX_OFFSET                = BSP_MISC_IRQ_MAX_OFFSET,
     86#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
     87#define BSP_MAIN_IRQ_NUMBER            (64)
     88#define BSP_LOWEST_OFFSET               (BSP_MICL_IRQ_LOWEST_OFFSET)
     89#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    10290
    10391  /* Main CPU interrupt cause (Low) */
    104   BSP_MAIN_TIMER0_1_IRQ         = BSP_MICL_IRQ_LOWEST_OFFSET+8,
    105   BSP_MAIN_PCI0_7_0             = BSP_MICL_IRQ_LOWEST_OFFSET+12,
    106   BSP_MAIN_PCI0_15_8            = BSP_MICL_IRQ_LOWEST_OFFSET+13,
    107   BSP_MAIN_PCI0_23_16           = BSP_MICL_IRQ_LOWEST_OFFSET+14,
    108   BSP_MAIN_PCI0_31_24           = BSP_MICL_IRQ_LOWEST_OFFSET+15,
    109   BSP_MAIN_PCI1_7_0             = BSP_MICL_IRQ_LOWEST_OFFSET+16,
    110   BSP_MAIN_PCI1_15_8            = BSP_MICL_IRQ_LOWEST_OFFSET+18,
    111   BSP_MAIN_PCI1_23_16           = BSP_MICL_IRQ_LOWEST_OFFSET+19,
    112   BSP_MAIN_PCI1_31_24           = BSP_MICL_IRQ_LOWEST_OFFSET+20,
     92#define BSP_MAIN_TIMER0_1_IRQ         (BSP_MICL_IRQ_LOWEST_OFFSET+8)
     93#define BSP_MAIN_PCI0_7_0             (BSP_MICL_IRQ_LOWEST_OFFSET+12)
     94#define BSP_MAIN_PCI0_15_8            (BSP_MICL_IRQ_LOWEST_OFFSET+13)
     95#define BSP_MAIN_PCI0_23_16           (BSP_MICL_IRQ_LOWEST_OFFSET+14)
     96#define BSP_MAIN_PCI0_31_24           (BSP_MICL_IRQ_LOWEST_OFFSET+15)
     97#define BSP_MAIN_PCI1_7_0             (BSP_MICL_IRQ_LOWEST_OFFSET+16)
     98#define BSP_MAIN_PCI1_15_8            (BSP_MICL_IRQ_LOWEST_OFFSET+18)
     99#define BSP_MAIN_PCI1_23_16           (BSP_MICL_IRQ_LOWEST_OFFSET+19)
     100#define BSP_MAIN_PCI1_31_24           (BSP_MICL_IRQ_LOWEST_OFFSET+20)
    113101
    114102
    115103  /* Main CPU interrupt cause (High) */
    116   BSP_MAIN_ETH0_IRQ             = BSP_MICH_IRQ_LOWEST_OFFSET,
    117   BSP_MAIN_ETH1_IRQ             = BSP_MICH_IRQ_LOWEST_OFFSET+1,
    118   BSP_MAIN_ETH2_IRQ             = BSP_MICH_IRQ_LOWEST_OFFSET+2,
    119   BSP_MAIN_GPP7_0_IRQ           = BSP_MICH_IRQ_LOWEST_OFFSET+24,
    120   BSP_MAIN_GPP15_8_IRQ          = BSP_MICH_IRQ_LOWEST_OFFSET+25,
    121   BSP_MAIN_GPP23_16_IRQ         = BSP_MICH_IRQ_LOWEST_OFFSET+26,
    122   BSP_MAIN_GPP31_24_IRQ         = BSP_MICH_IRQ_LOWEST_OFFSET+27,
     104#define BSP_MAIN_ETH0_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET)
     105#define BSP_MAIN_ETH1_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET+1)
     106#define BSP_MAIN_ETH2_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET+2)
     107#define BSP_MAIN_GPP7_0_IRQ           (BSP_MICH_IRQ_LOWEST_OFFSET+24)
     108#define BSP_MAIN_GPP15_8_IRQ          (BSP_MICH_IRQ_LOWEST_OFFSET+25)
     109#define BSP_MAIN_GPP23_16_IRQ         (BSP_MICH_IRQ_LOWEST_OFFSET+26)
     110#define BSP_MAIN_GPP31_24_IRQ         (BSP_MICH_IRQ_LOWEST_OFFSET+27)
    123111
    124112  /* on the MVME5500, these are the GT64260B external GPP0 interrupt */
    125   BSP_ISA_UART_COM2_IRQ         = BSP_GPP_IRQ_LOWEST_OFFSET,
    126   BSP_ISA_UART_COM1_IRQ         = BSP_GPP_IRQ_LOWEST_OFFSET,
    127   BSP_GPP8_IRQ_OFFSET           = BSP_GPP_IRQ_LOWEST_OFFSET+8,
    128   BSP_GPP_PMC1_INTA             = BSP_GPP8_IRQ_OFFSET,
    129   BSP_GPP16_IRQ_OFFSET          = BSP_GPP_IRQ_LOWEST_OFFSET+16,
    130   BSP_GPP24_IRQ_OFFSET          = BSP_GPP_IRQ_LOWEST_OFFSET+24,
    131   BSP_GPP_VME_VLINT0            = BSP_GPP_IRQ_LOWEST_OFFSET+12,
    132   BSP_GPP_VME_VLINT1            = BSP_GPP_IRQ_LOWEST_OFFSET+13,
    133   BSP_GPP_VME_VLINT2            = BSP_GPP_IRQ_LOWEST_OFFSET+14,
    134   BSP_GPP_VME_VLINT3            = BSP_GPP_IRQ_LOWEST_OFFSET+15,
    135   BSP_GPP_PMC2_INTA             = BSP_GPP_IRQ_LOWEST_OFFSET+16,
    136   BSP_GPP_82544_IRQ             = BSP_GPP_IRQ_LOWEST_OFFSET+20,
    137   BSP_GPP_WDT_NMI_IRQ           = BSP_GPP_IRQ_LOWEST_OFFSET+24,
    138   BSP_GPP_WDT_EXP_IRQ           = BSP_GPP_IRQ_LOWEST_OFFSET+25,
     113#define BSP_ISA_UART_COM2_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET)
     114#define BSP_ISA_UART_COM1_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET)
     115#define BSP_GPP8_IRQ_OFFSET             (BSP_GPP_IRQ_LOWEST_OFFSET+8)
     116#define BSP_GPP_PMC1_INTA               (BSP_GPP8_IRQ_OFFSET)
     117#define BSP_GPP16_IRQ_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET+16)
     118#define BSP_GPP24_IRQ_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET+24)
     119#define BSP_GPP_VME_VLINT0            (BSP_GPP_IRQ_LOWEST_OFFSET+12)
     120#define BSP_GPP_VME_VLINT1            (BSP_GPP_IRQ_LOWEST_OFFSET+13)
     121#define BSP_GPP_VME_VLINT2            (BSP_GPP_IRQ_LOWEST_OFFSET+14)
     122#define BSP_GPP_VME_VLINT3            (BSP_GPP_IRQ_LOWEST_OFFSET+15)
     123#define BSP_GPP_PMC2_INTA             (BSP_GPP_IRQ_LOWEST_OFFSET+16)
     124#define BSP_GPP_82544_IRQ             (BSP_GPP_IRQ_LOWEST_OFFSET+20)
     125#define BSP_GPP_WDT_NMI_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET+24)
     126#define BSP_GPP_WDT_EXP_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET+25)
    139127
    140128 /*
    141129   * Some Processor execption handled as rtems IRQ symbolic name definition
    142130   */
    143   BSP_DECREMENTER               =       BSP_PROCESSOR_IRQ_LOWEST_OFFSET
    144 }rtems_irq_symbolic_name;
    145 
    146 /*
    147  * Type definition for RTEMS managed interrupts
    148  */
    149 typedef unsigned char  rtems_irq_prio;
     131#define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    150132
    151133typedef unsigned int rtems_GTirq_masks;
     
    153135extern rtems_GTirq_masks GT_GPPirq_cache;
    154136extern rtems_GTirq_masks GT_MAINirqLO_cache, GT_MAINirqHI_cache;
    155 
    156 struct  __rtems_irq_connect_data__;     /* forward declaratiuon */
    157 
    158 typedef void *rtems_irq_hdl_param;
    159 typedef void (*rtems_irq_hdl)           (rtems_irq_hdl_param);
    160 typedef void (*rtems_irq_ack)           (void);
    161 typedef void (*rtems_irq_enable)        (const struct __rtems_irq_connect_data__*);
    162 typedef void (*rtems_irq_disable)       (const struct __rtems_irq_connect_data__*);
    163 typedef int  (*rtems_irq_is_enabled)    (const struct __rtems_irq_connect_data__*);
    164 
    165 typedef struct __rtems_irq_connect_data__ {
    166       /*
    167        * IRQ line
    168        */
    169       rtems_irq_symbolic_name   name;
    170       /*
    171        * handler. See comment on handler properties below in function prototype.
    172        */
    173       rtems_irq_hdl             hdl;
    174      /*
    175       * Handler handle to store private data
    176       */
    177       rtems_irq_hdl_param               handle;
    178       /*
    179        * function for enabling interrupts at device level (ONLY!).
    180        * The BSP code will automatically enable it at i8259s level and openpic level.
    181        * RATIONALE : anyway such code has to exist in current driver code.
    182        * It is usually called immediately AFTER connecting the interrupt handler.
    183        * RTEMS may well need such a function when restoring normal interrupt
    184        * processing after a debug session.
    185        *
    186        */
    187       rtems_irq_enable          on;     
    188       /*
    189        * function for disabling interrupts at device level (ONLY!).
    190        * The code will disable it at i8259s level. RATIONALE : anyway
    191        * such code has to exist for clean shutdown. It is usually called
    192        * BEFORE disconnecting the interrupt. RTEMS may well need such
    193        * a function when disabling normal interrupt processing for
    194        * a debug session. May well be a NOP function.
    195        */
    196       rtems_irq_disable         off;
    197       /*
    198        * function enabling to know what interrupt may currently occur
    199        * if someone manipulates the i8259s interrupt mask without care...
    200        */
    201       rtems_irq_is_enabled      isOn;
    202       /*
    203        *  Set to -1 for vectors forced to have only 1 handler
    204        */
    205       void *next_handler;
    206 
    207 }rtems_irq_connect_data;
    208 
    209 typedef struct {
    210   /*
    211    * size of all the table fields (*Tbl) described below.
    212    */
    213   unsigned int                  irqNb;
    214   /*
    215    * Default handler used when disconnecting interrupts.
    216    */
    217   rtems_irq_connect_data        defaultEntry;
    218   /*
    219    * Table containing initials/current value.
    220    */
    221   rtems_irq_connect_data*       irqHdlTbl;
    222   /*
    223    * actual value of BSP_ISA_IRQ_VECTOR_BASE...
    224    */
    225   rtems_irq_symbolic_name       irqBase;
    226   /*
    227    * software priorities associated with interrupts.
    228    * if irqPrio  [i]  >  intrPrio  [j]  it  means  that 
    229    * interrupt handler hdl connected for interrupt name i
    230    * will  not be interrupted by the handler connected for interrupt j
    231    * The interrupt source  will be physically masked at i8259 level.
    232    */
    233     rtems_irq_prio*             irqPrioTbl;
    234 }rtems_irq_global_settings;
    235 
    236 /*
    237  * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
    238  */
    239 /*
    240  * function to connect a particular irq handler. This hanlder will NOT be called
    241  * directly as the result of the corresponding interrupt. Instead, a RTEMS
    242  * irq prologue will be called that will :
    243  *
    244  *      1) save the C scratch registers,
    245  *      2) switch to a interrupt stack if the interrupt is not nested,
    246  *      3) store the current i8259s' interrupt masks
    247  *      4) modify them to disable the current interrupt at 8259 level (and may
    248  *      be others depending on software priorities)
    249  *      5) aknowledge the i8259s',
    250  *      6) demask the processor,
    251  *      7) call the application handler
    252  *
    253  * As a result the hdl function provided
    254  *
    255  *      a) can perfectly be written is C,
    256  *      b) may also well directly call the part of the RTEMS API that can be used
    257  *      from interrupt level,
    258  *      c) It only responsible for handling the jobs that need to be done at
    259  *      the device level including (aknowledging/re-enabling the interrupt at device,
    260  *      level, getting the data,...)
    261  *
    262  *      When returning from the function, the following will be performed by
    263  *      the RTEMS irq epilogue :
    264  *
    265  *      1) masks the interrupts again,
    266  *      2) restore the original i8259s' interrupt masks
    267  *      3) switch back on the orinal stack if needed,
    268  *      4) perform rescheduling when necessary,
    269  *      5) restore the C scratch registers...
    270  *      6) restore initial execution flow
    271  *
    272  */
    273 int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
    274 int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
    275 
    276 #define BSP_SHARED_HANDLER_SUPPORT      1
    277 
    278 /*
    279  * function to get the current RTEMS irq handler for ptr->name. It enables to
    280  * define hanlder chain...
    281  */
    282 int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
    283 /*
    284  * function to get disconnect the RTEMS irq handler for ptr->name.
    285  * This function checks that the value given is the current one for safety reason.
    286  * The user can use the previous function to get it.
    287  */
    288 int BSP_remove_rtems_irq_handler        (const rtems_irq_connect_data*);
    289 
    290 /*
    291  * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
    292  */
    293 /*
    294  * (Re) Initialize the RTEMS interrupt management.
    295  *
    296  * The result of calling this function will be the same as if each individual
    297  * handler (config->irqHdlTbl[i].hdl)  different from "config->defaultEntry.hdl"
    298  * has been individualy connected via
    299  *      BSP_install_rtems_irq_handler(&config->irqHdlTbl[i])
    300  * And each handler currently equal to config->defaultEntry.hdl
    301  * has been previously disconnected via
    302  *       BSP_remove_rtems_irq_handler (&config->irqHdlTbl[i])
    303  *
    304  * This is to say that all information given will be used and not just
    305  * only the space.
    306  *
    307  * CAUTION : the various table address contained in config will be used
    308  *           directly by the interrupt mangement code in order to save
    309  *           data size so they must stay valid after the call => they should
    310  *           not be modified or declared on a stack.
    311  */
    312 
    313 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
    314 /*
    315  * (Re) get info on current RTEMS interrupt management.
    316  */
    317 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
    318137
    319138void BSP_enable_main_irq(unsigned irqNum);
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