[b599faa] | 1 | /* |
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| 2 | * bsp.h -- contain BSP API definition. |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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[0c875c6a] | 7 | * found in the file LICENSE in this distribution or at |
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[b599faa] | 8 | * http://www.rtems.com/license/LICENSE. |
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| 9 | * |
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| 10 | * Adapted for the mvme3100 BSP by T. Straumann, 2007. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | #ifndef _BSP_H |
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| 15 | #define _BSP_H |
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| 16 | |
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| 17 | #include <bspopts.h> |
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| 18 | |
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| 19 | #include <rtems.h> |
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| 20 | #include <rtems/console.h> |
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| 21 | #include <libcpu/io.h> |
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| 22 | #include <rtems/clockdrv.h> |
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[43fa4fc] | 23 | #include <bsp/vectors.h> |
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[b599faa] | 24 | |
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| 25 | /* |
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| 26 | * confdefs.h overrides for this BSP: |
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| 27 | */ |
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[704e371] | 28 | #define CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK |
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[ac7af4a] | 29 | |
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[7347b0d] | 30 | #define BSP_INTERRUPT_STACK_SIZE (16 * 1024) |
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[b599faa] | 31 | |
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| 32 | /* |
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| 33 | * diagram illustrating the role of the configuration |
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| 34 | * constants |
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| 35 | * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible |
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| 36 | * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this |
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| 37 | * address being 'visible' or not!). |
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| 38 | * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME |
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| 39 | * _VME_A32_WIN0_ON_VME: VME address of that same window |
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| 40 | * |
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| 41 | * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between |
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| 42 | * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI |
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| 43 | * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to |
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| 44 | * the base address read from PCI config.space in order to translate that |
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| 45 | * into a CPU address. |
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| 46 | * |
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| 47 | * NOTE: VME addresses should NEVER be translated using these constants! |
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| 48 | * they are strictly for BSP internal use. Drivers etc. should use |
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| 49 | * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). |
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[ac7af4a] | 50 | * |
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[b599faa] | 51 | * CPU ADDR PCI_ADDR VME ADDR |
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[ac7af4a] | 52 | * |
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[b599faa] | 53 | * 00000000 XXXXXXXX XXXXXXXX |
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[ac7af4a] | 54 | * ^ ^ ........ |
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[b599faa] | 55 | * | | |
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| 56 | * | | e.g., RAM XXXXXXXX |
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| 57 | * | | 00000000 |
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| 58 | * | | ......... ^ |
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| 59 | * | | (possible offset | |
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| 60 | * | | between pci and XXXXXXXX | ...... |
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| 61 | * | | cpu addresses) | |
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| 62 | * | v | |
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| 63 | * | PCI_MEM_BASE -------------> 00000000 --------------- | |
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| 64 | * | ........ ........ ^ | |
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| 65 | * | invisible | | |
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| 66 | * | ........ from CPU | | |
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| 67 | * v | | |
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| 68 | * PCI_MEM_WIN0 ============= first visible PCI addr | | |
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| 69 | * | | |
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| 70 | * pci devices pci window | | |
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| 71 | * visible here v v |
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| 72 | * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME |
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| 73 | * vme window |
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| 74 | * VME devices hostbridge mapped by |
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| 75 | * visible here universe |
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| 76 | * ===================================================== |
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[ac7af4a] | 77 | * |
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[b599faa] | 78 | */ |
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| 79 | |
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| 80 | /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ |
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[ac7af4a] | 81 | #define _IO_BASE 0xe0000000 /* Motload's PCI IO base */ |
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[b599faa] | 82 | #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE |
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| 83 | /* address of our ram on the PCI bus */ |
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| 84 | #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET |
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| 85 | /* offset of pci memory as seen from the CPU */ |
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| 86 | #define PCI_MEM_BASE 0 |
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| 87 | /* where (in CPU addr. space) does the PCI window start */ |
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[ac7af4a] | 88 | #define PCI_MEM_WIN0 0x80000000 |
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[b599faa] | 89 | |
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| 90 | /* |
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| 91 | * Base address definitions for several devices |
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| 92 | */ |
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| 93 | |
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| 94 | #define BSP_OPEN_PIC_BASE_OFFSET 0x40000 |
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| 95 | #define BSP_OPEN_PIC_BIG_ENDIAN |
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| 96 | |
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| 97 | #define BSP_8540_CCSR_BASE (0xe1000000) |
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| 98 | |
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| 99 | #define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500) |
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| 100 | #define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600) |
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| 101 | #define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000) |
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| 102 | #define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004) |
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| 103 | #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((unsigned int*)(addr), (val)) |
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| 104 | |
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| 105 | #define BSP_CONSOLE_PORT BSP_UART_COM1 |
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| 106 | #define BSP_UART_BAUD_BASE (-9600) /* use existing divisor to determine clock rate */ |
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| 107 | #define BSP_UART_USE_SHARED_IRQS |
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| 108 | |
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| 109 | #define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) |
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| 110 | |
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| 111 | /* I2C Devices */ |
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| 112 | /* Note that the i2c addresses stated in the manual are |
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| 113 | * left-shifted by one bit. |
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| 114 | */ |
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| 115 | #define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ |
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| 116 | #define BSP_USR0_I2C_ADDR (0xA4>>1) /* the 1st user EEPROM */ |
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| 117 | #define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */ |
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| 118 | #define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ |
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| 119 | #define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */ |
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[ac7af4a] | 120 | |
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[b599faa] | 121 | #define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor |
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| 122 | |
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| 123 | #define BSP_I2C_BUS0_NAME "/dev/i2c0" |
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| 124 | |
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| 125 | #define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" |
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| 126 | #define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" |
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| 127 | #define BSP_I2C_USR1_EEPROM_NAME "usr1-eeprom" |
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| 128 | #define BSP_I2C_DS1621_NAME "ds1621" |
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| 129 | #define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME |
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| 130 | #define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" |
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| 131 | #define BSP_I2C_DS1375_RAW_NAME "ds1375-raw" |
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| 132 | #define BSP_I2C_RTC_RAW_NAME BSP_I2C_DS1375_RAW_NAME |
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| 133 | |
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| 134 | #define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) |
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| 135 | #define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) |
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| 136 | #define BSP_I2C_USR1_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR1_EEPROM_NAME) |
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| 137 | #define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) |
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| 138 | #define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME |
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| 139 | #define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) |
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| 140 | #define BSP_I2C_DS1375_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1375_RAW_NAME) |
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| 141 | |
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| 142 | /* Definitions useful for bootloader (netboot); where to find |
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| 143 | * boot/'environment' parameters. |
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| 144 | */ |
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| 145 | #define BSP_EEPROM_BOOTPARMS_NAME BSP_I2C_USR1_EEPROM_DEV_NAME |
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| 146 | #define BSP_EEPROM_BOOTPARMS_SIZE 1024 |
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| 147 | #define BSP_EEPROM_BOOTPARMS_OFFSET 0 |
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| 148 | #define BSP_BOOTPARMS_WRITE_ENABLE() do { BSP_eeprom_write_enable(); } while (0) |
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| 149 | #define BSP_BOOTPARMS_WRITE_DISABLE() do { BSP_eeprom_write_protect();} while (0) |
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| 150 | |
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| 151 | |
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| 152 | #ifdef __cplusplus |
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| 153 | extern "C" { |
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| 154 | #endif |
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[ac7af4a] | 155 | /* Initialize the I2C driver and register all devices |
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[b599faa] | 156 | * RETURNS 0 on success, -1 on error. |
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| 157 | * |
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| 158 | * Access to the VPD and user EEPROMS as well |
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| 159 | * as the ds1621 temperature sensor is possible |
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| 160 | * by means of file nodes |
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| 161 | * |
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| 162 | * /dev/i2c0.vpd-eeprom (read-only) |
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| 163 | * /dev/i2c0.usr-eeprom (read-write) |
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| 164 | * /dev/i2c0.usr1-eeprom (read-write) |
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| 165 | * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) |
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| 166 | * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) |
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| 167 | * /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375) |
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[ac7af4a] | 168 | * |
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[b599faa] | 169 | */ |
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| 170 | int |
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| 171 | BSP_i2c_initialize(); |
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| 172 | |
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| 173 | /* System Control Register */ |
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| 174 | #define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001) |
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[ac7af4a] | 175 | #define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5) |
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| 176 | #define BSP_MVME3100_SYS_CR_RESET (5<<5) |
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[b599faa] | 177 | #define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1) |
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| 178 | #define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0) |
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| 179 | |
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| 180 | /* LED support */ |
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| 181 | #define BSP_MVME3100_SYS_IND_REG ((volatile uint8_t *)0xe2000002) |
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| 182 | #define BSP_LED_BRD_FAIL (1<<0) |
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| 183 | #define BSP_LED_USR1 (1<<1) |
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| 184 | #define BSP_LED_USR2 (1<<2) |
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| 185 | #define BSP_LED_USR3 (1<<3) |
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| 186 | |
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| 187 | /* Flash CSR */ |
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| 188 | #define BSP_MVME3100_FLASH_CSR ((volatile uint8_t *)0xe2000003) |
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| 189 | #define BSP_MVME3100_FLASH_CSR_FLASH_RDY (1<<0) |
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| 190 | #define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL (1<<1) |
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| 191 | #define BSP_MVME3100_FLASH_CSR_F_WP_HW (1<<2) |
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| 192 | #define BSP_MVME3100_FLASH_CSR_F_WP_SW (1<<3) |
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| 193 | #define BSP_MVME3100_FLASH_CSR_MAP_SEL (1<<4) |
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| 194 | |
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| 195 | /* Phy interrupt detect */ |
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| 196 | #define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) |
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| 197 | |
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| 198 | /* Atomically set bits in a sys-register; The bits set in 'mask' |
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| 199 | * are set in the register others; are left unmodified. |
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| 200 | * |
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| 201 | * RETURNS: old state. |
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| 202 | * |
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| 203 | * NOTE : since BSP_setSysReg( reg, 0 ) does not make |
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| 204 | * any changes this call may be used |
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| 205 | * to read the current status w/o modifying it. |
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| 206 | */ |
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| 207 | uint8_t |
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| 208 | BSP_setSysReg(volatile uint8_t *r, uint8_t mask); |
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| 209 | |
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| 210 | /* Atomically clear bits in a sys-register; The bits set in 'mask' |
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| 211 | * are cleared in the register; others are left unmodified. |
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| 212 | * |
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| 213 | * RETURNS: old state. |
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| 214 | * |
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| 215 | * NOTE : since BSP_clrSysReg( reg, 0 ) does not make |
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| 216 | * any changes this call may be used |
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| 217 | * to read the current status w/o modifying it. |
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| 218 | */ |
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| 219 | |
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| 220 | uint8_t |
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| 221 | BSP_clrSysReg(volatile uint8_t *r, uint8_t mask); |
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| 222 | |
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| 223 | /* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */ |
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| 224 | |
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| 225 | /* Set write-protection for all EEPROM devices |
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| 226 | * RETURNS: old status |
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| 227 | */ |
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| 228 | uint8_t |
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| 229 | BSP_eeprom_write_protect(); |
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| 230 | |
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| 231 | /* Disengage write-protection for all EEPROM devices |
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| 232 | * RETURNS: old status |
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| 233 | */ |
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| 234 | uint8_t |
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| 235 | BSP_eeprom_write_enable(); |
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| 236 | |
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| 237 | /* Set LEDs that have their bit set in the mask |
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| 238 | * |
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| 239 | * RETURNS: old status. |
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| 240 | * |
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| 241 | * NOTE : since BSP_setLEDs( 0 ) does not make |
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| 242 | * any changes this call may be used |
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| 243 | * to read the current status w/o modifying it. |
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| 244 | */ |
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| 245 | uint8_t |
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| 246 | BSP_setLEDs(uint8_t mask); |
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| 247 | |
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| 248 | /* Clear LEDs that have their bit set in the mask |
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| 249 | * |
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| 250 | * RETURNS: old status |
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| 251 | * |
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| 252 | * NOTE: : see above (BSP_setLEDs) |
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| 253 | */ |
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| 254 | uint8_t |
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| 255 | BSP_clrLEDs(uint8_t mask); |
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| 256 | |
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| 257 | #if 0 |
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| 258 | #define outport_byte(port,value) outb(value,port) |
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| 259 | #define outport_word(port,value) outw(value,port) |
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| 260 | #define outport_long(port,value) outl(value,port) |
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| 261 | |
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| 262 | #define inport_byte(port,value) (value = inb(port)) |
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| 263 | #define inport_word(port,value) (value = inw(port)) |
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| 264 | #define inport_long(port,value) (value = inl(port)) |
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| 265 | #endif |
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| 266 | |
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| 267 | /* |
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| 268 | * Total memory using RESIDUAL DATA |
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| 269 | */ |
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| 270 | extern unsigned int BSP_mem_size; |
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| 271 | /* |
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| 272 | * PCI Bus Frequency |
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| 273 | */ |
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| 274 | extern unsigned int BSP_bus_frequency; |
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| 275 | /* |
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| 276 | * processor clock frequency |
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| 277 | */ |
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| 278 | extern unsigned int BSP_processor_frequency; |
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| 279 | /* |
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| 280 | * Time base divisior (how many tick for 1 second). |
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| 281 | */ |
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| 282 | extern unsigned int BSP_time_base_divisor; |
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[10a9260] | 283 | /* |
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| 284 | * The commandline as passed from the bootloader. |
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| 285 | */ |
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| 286 | extern char *BSP_commandline_string; |
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[b599faa] | 287 | |
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| 288 | #define BSP_Convert_decrementer( _value ) \ |
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| 289 | ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) |
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| 290 | |
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| 291 | extern rtems_configuration_table BSP_Configuration; |
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| 292 | extern void BSP_panic(char *s); |
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| 293 | /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ |
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| 294 | extern int BSP_disconnect_clock_handler (void); |
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| 295 | extern int BSP_connect_clock_handler (void); |
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| 296 | |
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| 297 | /* clear hostbridge errors |
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| 298 | * |
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| 299 | * NOTE: The routine returns always (-1) if 'enableMCP==1' |
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| 300 | * [semantics needed by libbspExt] if the MCP input is not wired. |
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| 301 | * It returns and clears the error bits of the PCI status register. |
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| 302 | * MCP support is disabled because: |
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| 303 | * a) the 2100 has no raven chip |
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| 304 | * b) the raven (2300) would raise machine check interrupts |
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| 305 | * on PCI config space access to empty slots. |
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| 306 | */ |
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| 307 | extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); |
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| 308 | extern void BSP_motload_pci_fixup(); |
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| 309 | |
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| 310 | struct rtems_bsdnet_ifconfig; |
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| 311 | |
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| 312 | int |
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| 313 | rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); |
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| 314 | |
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| 315 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "tse1" |
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| 316 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach |
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| 317 | |
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| 318 | #ifdef __cplusplus |
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| 319 | } |
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| 320 | #endif |
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| 321 | |
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| 322 | #endif |
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