RTEMS SIMD Support

SIMD Support in RTEMS

As of release 4.10 RTEMS supports managing the SIMD registers on select CPU architectures. I.e., SIMD registers are preserved across context switches and exceptions/interrupts. The support is automatically enabled if RTEMS is compiled for a CPU which features SIMD hardware. This is accomplished by using standardized CPP macros that are set by gcc when it generates code for a SIMD-capable CPU. E.g., when compiling for a 7400 powerpc (which has AltiVec?) or explicitly requesting AltiVec? (gcc's -maltivec flag) then gcc pre-defines the CPP macro ALTIVEC.

... to-be-continued ...