wiki:TBR/BSP/V320usc

V320usc

{{Infobox BSP |BSP_name = V320USC |image = v320usc.jpg |Manufacturer = QuickLogic Corp |Board_URL = References |Architecture = MIPS RISC |CPU_model = MIPS, SH3, SH4 |Monitor = uBoot, uMon |Simulator = No |Aliases = V320USC |RAM = Up to 1GB SDRAM }}

Overview

The V320USC Universal System Controller is a third-generation PCI product which integrates many functions needed in typical embedded systems. The USC reduces overall system cost by replacing a number of lower-integration support components with a single, highly integrated device. The PCI bus is an important standard used in todays embedded systems. While the V320USC addresses this requirement, it is also far more than a simple PCI interface. The USC controls the essential components of an embedded system, such as SDRAM memory, FLASH memory, and peripherals by using a flexible memory controller and peripheral control unit. As a system controller, the V320USC provides additional peripheral functions required in a typical embedded system. Two 32-bit general purpose timers can be individually configured as a pulse width modulator, rate generator, pulse counter, or hardwaresoftware triggered pulse generator Watchdog timer for graceful recovery from catastrophic program failures Heartbeat interrupt timer for RTOS interrupt generation Bus watch timer to prevent system hangs during accesses to undecoded regions Four-channel interrupt controller to generate either PCI or local CPU interrupts and interrupt cross-routing.

Specification

  • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus
  • Fully compliant with PCI 2.2 specification
  • Configurable for primary master, bus master, or target operation
  • SDRAM controller with support for Enhanced SDRAM
  • Up to 1 Kbyte burst access to (E)SDRAM from PCI, 32 bytes from local processor (MIPS mode)
  • 640 bytes of on-chip FIFO storage with Dynamic Bandwidth Allocation™ architecture
  • On-the-fly byte order (endian) conversion
  • I2O Ready™ ATU and messaging unit
  • Programmable chip select / peripheral device strobe generation
  • Hot Swap Ready (PICMG™ Hot Swap Specification 2.1)
  • Implementation of PCI Bus Power Management Interface Specification Version 1.0
  • 3.3V operation with 5V tolerant inputs
  • 208-pin PQFP package
  • Up to 75 MHz local bus clock with separate asynchronous PCI clock up to 50 MHz
  • Two 32-bit timers
  • Initialization through local processor, PCI or serial EEPROM

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.

Debugging

How do you debug code on this board? What gdb setup? BDM, stub, etc?

Test Reports

{{Test Report |Version = RTEMS Version |Date = Date |User = User |Report = reports that something happened. }}

References

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Last modified on Nov 28, 2010 at 9:35:24 PM Last modified on Nov 28, 2010, 9:35:24 PM